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Domy131097

LV3_traffic_light_CNTRL

Nov 24th, 2020
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  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3.  
  4. entity traffic_light_CNTRL is
  5. --TO DO 1 -> deklarirati ulaz "clk" (STD_LOGIC) i izlaze "segment" i "display" (STD_LOGIC_VECTOR) veličine 8 i 4 bita
  6. Port ( clk: IN STD_LOGIC;
  7. segment: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
  8. display: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
  9. );
  10. end traffic_light_CNTRL;
  11.  
  12. architecture Behavioral of traffic_light_CNTRL is
  13.  
  14. --TO DO 2 -> definirati konstante "timeR", "timeRY", "timeG", "timeY" i "timeMAX" tipa integer te im pridružiti odgovarajuće vrijednosti
  15. constant timeR: INTEGER := 5;
  16. constant timeRY: INTEGER := 1;
  17. constant timeG: INTEGER := 4;
  18. constant timeY: INTEGER := 2;
  19. constant timeMAX: INTEGER := 5;
  20.  
  21. --TO DO 3 -> definirati korisnički tip podataka naziva "state" koji može imati vrijednosti "R", "RY", "G" i "Y"
  22. TYPE state IS(R,RY,G,Y);
  23.  
  24. --TO DO 4 -> deklarirati signale "current_state" i "next_state" koji su tipa "state"
  25. SIGNAL current_state, next_state: state;
  26.  
  27. --TO DO 5 -> deklarirati signal "clk_div" koji je tipa STD_LOGIC
  28. SIGNAL clk_div: STD_LOGIC;
  29.  
  30. --TO DO 6 -> deklarirati signal "time_temp" koji je tipa integer i ima može poprimiti vrijednosti u rasponu od 0 do "timeMAX"
  31. SIGNAL time_temp: INTEGER RANGE 0 TO timeMAX;
  32.  
  33. begin
  34.  
  35. --TO DO 7 -> signalu "display" pridružiti vrijednost tako da se svjetla semafora prikazuju na pokazniku AN0
  36. display <= "1110";
  37.  
  38. --TO DO 8 -> instancirati generički djelitelj frekvencije na način da od ulaznog singala takta kreira signal takta frekvencije 1 Hz
  39. L1: entity work.generic_divider generic map(50_000_000) port map (clk, clk_div);
  40.  
  41. ----Lower section of FSM----
  42. process(clk_div)
  43. --TO DO 9 -> deklarirati varijablu "counter" koja može poprimiti vrijednosti u intervalu 0 do "timeMAX"
  44. variable counter: INTEGER RANGE 0 TO timeMAX;
  45. begin
  46. --TO DO 10 -> na rastući brid signala takta "clk_div" povećati varijablu "counter" za 1
  47. if(clk_div'EVENT AND clk_div = '1') then
  48. counter := counter + 1;
  49. --TO DO 11 -> ako varijabla "counter" ima vrijednost "time_temp" onda signalu "current_state" pridružiti vrijednost signala "next_state", a varijablu "counter" resetirati na 0
  50. if (counter >= time_temp) then
  51. current_state <= next_state;
  52. counter := 0;
  53. end if;
  54. end if;
  55. end process;
  56.  
  57. ----Upper section of FSM----
  58. process(current_state)
  59. begin
  60. case current_state is
  61. --TO DO 12 -> u ovisnosti o vrijednosti signala "current_state" signalima "segment", "time_temp" i "next_state" pridružiti odgovarajuće vrijednosti
  62. when R =>
  63. segment <= "11111110";
  64. time_temp <= timeR;
  65. next_state <= RY;
  66. when RY =>
  67. segment <= "10111110";
  68. time_temp <= timeRY;
  69. next_state <= G;
  70. when G =>
  71. segment <= "11110111";
  72. time_temp <= timeG;
  73. next_state <= Y;
  74. when Y =>
  75. segment <= "10111111";
  76. time_temp <= timeY;
  77. next_state <= R;
  78. end case;
  79. end process;
  80.  
  81. end Behavioral;
  82.  
  83.  
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