vdiv-sdnode.ll

; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32-V
; RUN: llc -mtriple=riscv32 -mattr=+m,+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32-ZVE64X
; RUN: llc -mtriple=riscv64 -mattr=+m,+v -target-abi=lp64 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64-V
; RUN: llc -mtriple=riscv64 -mattr=+m,+zve64x -target-abi=lp64 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64-ZVE64X

define <vscale x 2 x i64> @vdiv_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
; RV32-V-LABEL: vdiv_vi_nxv2i64_0:
; RV32-V:       # %bb.0:
; RV32-V-NEXT:    addi sp, sp, -16
; RV32-V-NEXT:    .cfi_def_cfa_offset 16
; RV32-V-NEXT:    lui a0, 748983
; RV32-V-NEXT:    addi a0, a0, -586
; RV32-V-NEXT:    sw a0, 12(sp)
; RV32-V-NEXT:    lui a0, 898779
; RV32-V-NEXT:    addi a0, a0, 1755
; RV32-V-NEXT:    sw a0, 8(sp)
; RV32-V-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
; RV32-V-NEXT:    addi a0, sp, 8
; RV32-V-NEXT:    vlse64.v v10, (a0), zero
; RV32-V-NEXT:    vmulh.vv v8, v8, v10
; RV32-V-NEXT:    li a0, 63
; RV32-V-NEXT:    vsrl.vx v10, v8, a0
; RV32-V-NEXT:    vsra.vi v8, v8, 1
; RV32-V-NEXT:    vadd.vv v8, v8, v10
; RV32-V-NEXT:    addi sp, sp, 16
; RV32-V-NEXT:    ret
;
; RV32-ZVE64X-LABEL: vdiv_vi_nxv2i64_0:
; RV32-ZVE64X:       # %bb.0:
; RV32-ZVE64X-NEXT:    li a0, -7
; RV32-ZVE64X-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
; RV32-ZVE64X-NEXT:    vdiv.vx v8, v8, a0
; RV32-ZVE64X-NEXT:    ret
;
; RV64-V-LABEL: vdiv_vi_nxv2i64_0:
; RV64-V:       # %bb.0:
; RV64-V-NEXT:    lui a0, %hi(.LCPI61_0)
; RV64-V-NEXT:    ld a0, %lo(.LCPI61_0)(a0)
; RV64-V-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
; RV64-V-NEXT:    vmulh.vx v8, v8, a0
; RV64-V-NEXT:    li a0, 63
; RV64-V-NEXT:    vsrl.vx v10, v8, a0
; RV64-V-NEXT:    vsra.vi v8, v8, 1
; RV64-V-NEXT:    vadd.vv v8, v8, v10
; RV64-V-NEXT:    ret
;
; RV64-ZVE64X-LABEL: vdiv_vi_nxv2i64_0:
; RV64-ZVE64X:       # %bb.0:
; RV64-ZVE64X-NEXT:    li a0, -7
; RV64-ZVE64X-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
; RV64-ZVE64X-NEXT:    vdiv.vx v8, v8, a0
; RV64-ZVE64X-NEXT:    ret
  %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
  %vc = sdiv <vscale x 2 x i64> %va, %splat
  ret <vscale x 2 x i64> %vc
}