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vdiv-sdnode.ll

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Jan 23rd, 2022
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  1. ; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32-V
  2. ; RUN: llc -mtriple=riscv32 -mattr=+m,+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32-ZVE64X
  3. ; RUN: llc -mtriple=riscv64 -mattr=+m,+v -target-abi=lp64 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64-V
  4. ; RUN: llc -mtriple=riscv64 -mattr=+m,+zve64x -target-abi=lp64 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64-ZVE64X
  5.  
  6. define <vscale x 2 x i64> @vdiv_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
  7. ; RV32-V-LABEL: vdiv_vi_nxv2i64_0:
  8. ; RV32-V: # %bb.0:
  9. ; RV32-V-NEXT: addi sp, sp, -16
  10. ; RV32-V-NEXT: .cfi_def_cfa_offset 16
  11. ; RV32-V-NEXT: lui a0, 748983
  12. ; RV32-V-NEXT: addi a0, a0, -586
  13. ; RV32-V-NEXT: sw a0, 12(sp)
  14. ; RV32-V-NEXT: lui a0, 898779
  15. ; RV32-V-NEXT: addi a0, a0, 1755
  16. ; RV32-V-NEXT: sw a0, 8(sp)
  17. ; RV32-V-NEXT: vsetvli a0, zero, e64, m2, ta, mu
  18. ; RV32-V-NEXT: addi a0, sp, 8
  19. ; RV32-V-NEXT: vlse64.v v10, (a0), zero
  20. ; RV32-V-NEXT: vmulh.vv v8, v8, v10
  21. ; RV32-V-NEXT: li a0, 63
  22. ; RV32-V-NEXT: vsrl.vx v10, v8, a0
  23. ; RV32-V-NEXT: vsra.vi v8, v8, 1
  24. ; RV32-V-NEXT: vadd.vv v8, v8, v10
  25. ; RV32-V-NEXT: addi sp, sp, 16
  26. ; RV32-V-NEXT: ret
  27. ;
  28. ; RV32-ZVE64X-LABEL: vdiv_vi_nxv2i64_0:
  29. ; RV32-ZVE64X: # %bb.0:
  30. ; RV32-ZVE64X-NEXT: li a0, -7
  31. ; RV32-ZVE64X-NEXT: vsetvli a1, zero, e64, m2, ta, mu
  32. ; RV32-ZVE64X-NEXT: vdiv.vx v8, v8, a0
  33. ; RV32-ZVE64X-NEXT: ret
  34. ;
  35. ; RV64-V-LABEL: vdiv_vi_nxv2i64_0:
  36. ; RV64-V: # %bb.0:
  37. ; RV64-V-NEXT: lui a0, %hi(.LCPI61_0)
  38. ; RV64-V-NEXT: ld a0, %lo(.LCPI61_0)(a0)
  39. ; RV64-V-NEXT: vsetvli a1, zero, e64, m2, ta, mu
  40. ; RV64-V-NEXT: vmulh.vx v8, v8, a0
  41. ; RV64-V-NEXT: li a0, 63
  42. ; RV64-V-NEXT: vsrl.vx v10, v8, a0
  43. ; RV64-V-NEXT: vsra.vi v8, v8, 1
  44. ; RV64-V-NEXT: vadd.vv v8, v8, v10
  45. ; RV64-V-NEXT: ret
  46. ;
  47. ; RV64-ZVE64X-LABEL: vdiv_vi_nxv2i64_0:
  48. ; RV64-ZVE64X: # %bb.0:
  49. ; RV64-ZVE64X-NEXT: li a0, -7
  50. ; RV64-ZVE64X-NEXT: vsetvli a1, zero, e64, m2, ta, mu
  51. ; RV64-ZVE64X-NEXT: vdiv.vx v8, v8, a0
  52. ; RV64-ZVE64X-NEXT: ret
  53. %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
  54. %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
  55. %vc = sdiv <vscale x 2 x i64> %va, %splat
  56. ret <vscale x 2 x i64> %vc
  57. }
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