API tools faq
paste
Advertisement
Guest User

Untitled

a guest
Jun 14th, 2021
103
0
Never
Add comment
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
text 31.81 KB | None | 0 0
raw download clone embed print report
  1. [piotro@minimyth-armv8 allwinner]$ cat sun50i-h616.dtsi
  2. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  3. // Copyright (C) 2020 Arm Ltd.
  4. // based on the H6 dtsi, which is:
  5. // Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
  6.  
  7. #include <dt-bindings/interrupt-controller/arm-gic.h>
  8. #include <dt-bindings/clock/sun50i-h616-ccu.h>
  9. #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
  10. #include <dt-bindings/clock/sun8i-de2.h>
  11. #include <dt-bindings/clock/sun8i-tcon-top.h>
  12. #include <dt-bindings/reset/sun50i-h616-ccu.h>
  13. #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
  14. #include <dt-bindings/reset/sun8i-de2.h>
  15. #include <dt-bindings/thermal/thermal.h>
  16.  
  17. / {
  18. interrupt-parent = <&gic>;
  19. #address-cells = <2>;
  20. #size-cells = <2>;
  21.  
  22. cpus {
  23. #address-cells = <1>;
  24. #size-cells = <0>;
  25.  
  26. cpu0: cpu@0 {
  27. compatible = "arm,cortex-a53";
  28. device_type = "cpu";
  29. reg = <0>;
  30. enable-method = "psci";
  31. clocks = <&ccu CLK_CPUX>;
  32. clock-latency-ns = <244144>; /* 8 32k periods */
  33. operating-points-v2 = <&cpu_opp_table>;
  34. #cooling-cells = <2>;
  35. };
  36.  
  37. cpu1: cpu@1 {
  38. compatible = "arm,cortex-a53";
  39. device_type = "cpu";
  40. reg = <1>;
  41. enable-method = "psci";
  42. clocks = <&ccu CLK_CPUX>;
  43. clock-latency-ns = <244144>; /* 8 32k periods */
  44. //operating-points-v2 = <&cpu_opp_table>;
  45. #cooling-cells = <2>;
  46. };
  47.  
  48. cpu2: cpu@2 {
  49. compatible = "arm,cortex-a53";
  50. device_type = "cpu";
  51. reg = <2>;
  52. enable-method = "psci";
  53. clocks = <&ccu CLK_CPUX>;
  54. clock-latency-ns = <244144>; /* 8 32k periods */
  55. //operating-points-v2 = <&cpu_opp_table>;
  56. #cooling-cells = <2>;
  57. };
  58.  
  59. cpu3: cpu@3 {
  60. compatible = "arm,cortex-a53";
  61. device_type = "cpu";
  62. reg = <3>;
  63. enable-method = "psci";
  64. clocks = <&ccu CLK_CPUX>;
  65. clock-latency-ns = <244144>; /* 8 32k periods */
  66. //operating-points-v2 = <&cpu_opp_table>;
  67. #cooling-cells = <2>;
  68. };
  69. };
  70.  
  71. de: display-engine {
  72. compatible = "allwinner,sun50i-h6-display-engine";
  73. allwinner,pipelines = <&mixer0>;
  74. status = "disabled";
  75. };
  76.  
  77. reserved-memory {
  78. #address-cells = <2>;
  79. #size-cells = <2>;
  80. ranges;
  81.  
  82. /* 512KiB reserved for ARM Trusted Firmware (BL31) */
  83. secmon_reserved: secmon@40000000 {
  84. reg = <0x0 0x40000000 0x0 0x80000>;
  85. no-map;
  86. };
  87. };
  88.  
  89. osc24M: osc24M_clk {
  90. #clock-cells = <0>;
  91. compatible = "fixed-clock";
  92. clock-frequency = <24000000>;
  93. clock-output-names = "osc24M";
  94. };
  95.  
  96. pmu {
  97. compatible = "arm,cortex-a53-pmu";
  98. interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
  99. <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
  100. <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
  101. <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
  102. interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  103. };
  104.  
  105. psci {
  106. compatible = "arm,psci-0.2";
  107. method = "smc";
  108. };
  109.  
  110. timer {
  111. compatible = "arm,armv8-timer";
  112. arm,no-tick-in-suspend;
  113. interrupts = <GIC_PPI 13
  114. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  115. <GIC_PPI 14
  116. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  117. <GIC_PPI 11
  118. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  119. <GIC_PPI 10
  120. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  121. };
  122.  
  123. soc {
  124. compatible = "simple-bus";
  125. #address-cells = <1>;
  126. #size-cells = <1>;
  127. ranges = <0x0 0x0 0x0 0x40000000>;
  128.  
  129. bus@1000000 {
  130. compatible = "allwinner,sun50i-h616-de33",
  131. "allwinner,sun50i-a64-de2";
  132. reg = <0x1000000 0x400000>;
  133. allwinner,sram = <&de3_sram 1>;
  134. #address-cells = <1>;
  135. #size-cells = <1>;
  136. ranges = <0 0x1000000 0x400000>;
  137.  
  138. display_clocks: clock@8000 {
  139. compatible = "allwinner,sun50i-h616-de33-clk";
  140. reg = <0x8000 0x100>;
  141. clocks = <&ccu CLK_DE>, <&ccu CLK_BUS_DE>;
  142. clock-names = "mod", "bus";
  143. resets = <&ccu RST_BUS_DE>;
  144. #clock-cells = <1>;
  145. #reset-cells = <1>;
  146. };
  147.  
  148. mixer0: mixer@100000 {
  149. compatible = "allwinner,sun50i-h616-de33-mixer-0";
  150. reg = <0x100000 0x100000>,
  151. <0x8100 0x40>,
  152. <0x280000 0x20000>;
  153. clocks = <&display_clocks CLK_BUS_MIXER0>,
  154. <&display_clocks CLK_MIXER0>;
  155. clock-names = "bus", "mod";
  156. resets = <&display_clocks RST_MIXER0>;
  157. iommus = <&iommu 0>;
  158.  
  159. ports {
  160. #address-cells = <1>;
  161. #size-cells = <0>;
  162.  
  163. mixer0_out: port@1 {
  164. reg = <1>;
  165.  
  166. mixer0_out_tcon_top_mixer0: endpoint {
  167. remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
  168. };
  169. };
  170. };
  171. };
  172. };
  173.  
  174. syscon: syscon@3000000 {
  175. compatible = "allwinner,sun50i-h616-system-control";
  176. reg = <0x03000000 0x1000>;
  177. #address-cells = <1>;
  178. #size-cells = <1>;
  179. ranges;
  180.  
  181. sram_a2: sram@100000 {
  182. compatible = "mmio-sram";
  183. reg = <0x00100000 0x18000>;
  184. #address-cells = <1>;
  185. #size-cells = <1>;
  186. ranges = <0 0x00100000 0x18000>;
  187.  
  188. scpi_sram: scpi-sram@17c00 {
  189. compatible = "arm,scp-shmem";
  190. reg = <0x17c00 0x200>;
  191. };
  192. };
  193.  
  194. sram_c: sram@28000 {
  195. compatible = "mmio-sram";
  196. reg = <0x00028000 0x30000>;
  197. #address-cells = <1>;
  198. #size-cells = <1>;
  199. ranges = <0 0x00028000 0x30000>;
  200.  
  201. de3_sram: sram-section@0 {
  202. compatible = "allwinner,sun50i-h616-sram-c",
  203. "allwinner,sun50i-a64-sram-c";
  204. reg = <0x0000 0x1e000>;
  205. };
  206. };
  207.  
  208. sram_c1: sram@1a00000 {
  209. compatible = "mmio-sram";
  210. reg = <0x01a00000 0x200000>;
  211. #address-cells = <1>;
  212. #size-cells = <1>;
  213. ranges = <0 0x01a00000 0x200000>;
  214.  
  215. ve_sram: sram-section@0 {
  216. compatible = "allwinner,sun50i-h616-sram-c1",
  217. "allwinner,sun4i-a10-sram-c1";
  218. reg = <0x000000 0x200000>;
  219. };
  220. };
  221.  
  222. };
  223.  
  224. ccu: clock@3001000 {
  225. compatible = "allwinner,sun50i-h616-ccu";
  226. reg = <0x03001000 0x1000>;
  227. clocks = <&osc24M>, <&rtc 0>, <&rtc 2>;
  228. clock-names = "hosc", "losc", "iosc";
  229. #clock-cells = <1>;
  230. #reset-cells = <1>;
  231. };
  232.  
  233. sid: efuse@3006000 {
  234. compatible = "allwinner,sun50i-h616-sid";
  235. reg = <0x03006000 0x1000>;
  236. #address-cells = <1>;
  237. #size-cells = <1>;
  238.  
  239. cpu_speed_grade: cpu-speed-grade@00 {
  240. reg = <0x00 0x02>;
  241. };
  242.  
  243. ths_calibration: thermal-sensor-calibration@14 {
  244. reg = <0x14 0x8>;
  245. };
  246. };
  247.  
  248. watchdog: watchdog@30090a0 {
  249. compatible = "allwinner,sun50i-h616-wdt",
  250. "allwinner,sun6i-a31-wdt";
  251. reg = <0x030090a0 0x20>;
  252. interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
  253. clocks = <&osc24M>;
  254. status = "okay";
  255. };
  256.  
  257. pio: pinctrl@300b000 {
  258. compatible = "allwinner,sun50i-h616-pinctrl";
  259. reg = <0x0300b000 0x400>;
  260. interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
  261. <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
  262. <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
  263. <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
  264. <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
  265. <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
  266. <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
  267. <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
  268. clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>;
  269. clock-names = "apb", "hosc", "losc";
  270. gpio-controller;
  271. #gpio-cells = <3>;
  272. interrupt-controller;
  273. #interrupt-cells = <3>;
  274.  
  275. ext_rgmii_pins: rgmii-pins {
  276. pins = "PI0", "PI1", "PI2", "PI3", "PI4",
  277. "PI5", "PI7", "PI8", "PI9", "PI10",
  278. "PI11", "PI12", "PI13", "PI14", "PI15",
  279. "PI16";
  280. function = "emac0";
  281. drive-strength = <40>;
  282. };
  283.  
  284. rmii_pins: rmii-pins {
  285. pins = "PA0", "PA1", "PA2", "PA3", "PA4",
  286. "PA5", "PA6", "PA7", "PA8", "PA9";
  287. function = "emac1";
  288. drive-strength = <40>;
  289. };
  290.  
  291. i2c0_pins: i2c0-pins {
  292. pins = "PI6", "PI7";
  293. function = "i2c0";
  294. };
  295.  
  296. i2c3_ph_pins: i2c3-ph-pins {
  297. pins = "PH4", "PH5";
  298. function = "i2c3";
  299. };
  300.  
  301. ir_rx_pin: ir_rx_pin {
  302. pins = "PH10";
  303. function = "ir_rx";
  304. };
  305.  
  306. mmc0_pins: mmc0-pins {
  307. pins = "PF0", "PF1", "PF2", "PF3",
  308. "PF4", "PF5";
  309. function = "mmc0";
  310. drive-strength = <30>;
  311. bias-pull-up;
  312. };
  313.  
  314. mmc1_pins: mmc1-pins {
  315. pins = "PG0", "PG1", "PG2", "PG3",
  316. "PG4", "PG5";
  317. function = "mmc1";
  318. drive-strength = <30>;
  319. bias-pull-up;
  320. };
  321.  
  322. mmc2_pins: mmc2-pins {
  323. pins = "PC0", "PC1", "PC5", "PC6",
  324. "PC8", "PC9", "PC10", "PC11",
  325. "PC13", "PC14", "PC15", "PC16";
  326. function = "mmc2";
  327. drive-strength = <30>;
  328. bias-pull-up;
  329. };
  330.  
  331. spi0_pins: spi0-pins {
  332. pins = "PC0", "PC2", "PC3", "PC4";
  333. function = "spi0";
  334. };
  335.  
  336. spi1_pins: spi1-pins {
  337. pins = "PH6", "PH7", "PH8";
  338. function = "spi1";
  339. };
  340.  
  341. spi1_cs_pin: spi1-cs-pin {
  342. pins = "PH5";
  343. function = "spi1";
  344. };
  345.  
  346. uart0_ph_pins: uart0-ph-pins {
  347. pins = "PH0", "PH1";
  348. function = "uart0";
  349. };
  350.  
  351. uart1_pins: uart1-pins {
  352. pins = "PG6", "PG7";
  353. function = "uart1";
  354. };
  355.  
  356. uart1_rts_cts_pins: uart1-rts-cts-pins {
  357. pins = "PG8", "PG9";
  358. function = "uart1";
  359. };
  360. };
  361.  
  362. gic: interrupt-controller@3021000 {
  363. compatible = "arm,gic-400";
  364. reg = <0x03021000 0x1000>,
  365. <0x03022000 0x2000>,
  366. <0x03024000 0x2000>,
  367. <0x03026000 0x2000>;
  368. interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  369. interrupt-controller;
  370. #interrupt-cells = <3>;
  371. };
  372.  
  373. iommu: iommu@30f0000 {
  374. compatible = "allwinner,sun50i-h616-iommu";
  375. reg = <0x030f0000 0x10000>;
  376. interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
  377. clocks = <&ccu CLK_BUS_IOMMU>;
  378. resets = <&ccu RST_BUS_IOMMU>;
  379. #iommu-cells = <1>;
  380. status = "okay";
  381. };
  382.  
  383. mmc0: mmc@4020000 {
  384. compatible = "allwinner,sun50i-h616-mmc",
  385. "allwinner,sun50i-a100-mmc";
  386. reg = <0x04020000 0x1000>;
  387. clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
  388. clock-names = "ahb", "mmc";
  389. resets = <&ccu RST_BUS_MMC0>;
  390. reset-names = "ahb";
  391. interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  392. pinctrl-names = "default";
  393. pinctrl-0 = <&mmc0_pins>;
  394. status = "disabled";
  395. cap-sd-highspeed;
  396. cap-mmc-highspeed;
  397. mmc-ddr-3_3v;
  398. mmc-ddr-1_8v;
  399. cap-sdio-irq;
  400. #address-cells = <1>;
  401. #size-cells = <0>;
  402. };
  403.  
  404. mmc1: mmc@4021000 {
  405. compatible = "allwinner,sun50i-h616-mmc",
  406. "allwinner,sun50i-a100-mmc";
  407. reg = <0x04021000 0x1000>;
  408. clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
  409. clock-names = "ahb", "mmc";
  410. resets = <&ccu RST_BUS_MMC1>;
  411. reset-names = "ahb";
  412. interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
  413. pinctrl-names = "default";
  414. pinctrl-0 = <&mmc1_pins>;
  415. status = "disabled";
  416. cap-sd-highspeed;
  417. cap-mmc-highspeed;
  418. mmc-ddr-3_3v;
  419. mmc-ddr-1_8v;
  420. cap-sdio-irq;
  421. #address-cells = <1>;
  422. #size-cells = <0>;
  423. };
  424.  
  425. mmc2: mmc@4022000 {
  426. compatible = "allwinner,sun50i-h616-emmc",
  427. "allwinner,sun50i-a100-emmc";
  428. reg = <0x04022000 0x1000>;
  429. clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
  430. clock-names = "ahb", "mmc";
  431. resets = <&ccu RST_BUS_MMC2>;
  432. reset-names = "ahb";
  433. interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  434. pinctrl-names = "default";
  435. pinctrl-0 = <&mmc2_pins>;
  436. status = "disabled";
  437. cap-sd-highspeed;
  438. cap-mmc-highspeed;
  439. mmc-ddr-3_3v;
  440. mmc-ddr-1_8v;
  441. cap-sdio-irq;
  442. #address-cells = <1>;
  443. #size-cells = <0>;
  444. };
  445.  
  446. uart0: serial@5000000 {
  447. compatible = "snps,dw-apb-uart";
  448. reg = <0x05000000 0x400>;
  449. interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
  450. reg-shift = <2>;
  451. reg-io-width = <4>;
  452. clocks = <&ccu CLK_BUS_UART0>;
  453. resets = <&ccu RST_BUS_UART0>;
  454. status = "disabled";
  455. };
  456.  
  457. uart1: serial@5000400 {
  458. compatible = "snps,dw-apb-uart";
  459. reg = <0x05000400 0x400>;
  460. interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  461. reg-shift = <2>;
  462. reg-io-width = <4>;
  463. clocks = <&ccu CLK_BUS_UART1>;
  464. resets = <&ccu RST_BUS_UART1>;
  465. status = "disabled";
  466. };
  467.  
  468. uart2: serial@5000800 {
  469. compatible = "snps,dw-apb-uart";
  470. reg = <0x05000800 0x400>;
  471. interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
  472. reg-shift = <2>;
  473. reg-io-width = <4>;
  474. clocks = <&ccu CLK_BUS_UART2>;
  475. resets = <&ccu RST_BUS_UART2>;
  476. status = "disabled";
  477. };
  478.  
  479. uart3: serial@5000c00 {
  480. compatible = "snps,dw-apb-uart";
  481. reg = <0x05000c00 0x400>;
  482. interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  483. reg-shift = <2>;
  484. reg-io-width = <4>;
  485. clocks = <&ccu CLK_BUS_UART3>;
  486. resets = <&ccu RST_BUS_UART3>;
  487. status = "disabled";
  488. };
  489.  
  490. uart4: serial@5001000 {
  491. compatible = "snps,dw-apb-uart";
  492. reg = <0x05001000 0x400>;
  493. interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  494. reg-shift = <2>;
  495. reg-io-width = <4>;
  496. clocks = <&ccu CLK_BUS_UART4>;
  497. resets = <&ccu RST_BUS_UART4>;
  498. status = "disabled";
  499. };
  500.  
  501. uart5: serial@5001400 {
  502. compatible = "snps,dw-apb-uart";
  503. reg = <0x05001400 0x400>;
  504. interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  505. reg-shift = <2>;
  506. reg-io-width = <4>;
  507. clocks = <&ccu CLK_BUS_UART5>;
  508. resets = <&ccu RST_BUS_UART5>;
  509. status = "disabled";
  510. };
  511.  
  512. i2c0: i2c@5002000 {
  513. compatible = "allwinner,sun50i-h616-i2c",
  514. "allwinner,sun6i-a31-i2c";
  515. reg = <0x05002000 0x400>;
  516. interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
  517. clocks = <&ccu CLK_BUS_I2C0>;
  518. resets = <&ccu RST_BUS_I2C0>;
  519. pinctrl-names = "default";
  520. pinctrl-0 = <&i2c0_pins>;
  521. status = "disabled";
  522. #address-cells = <1>;
  523. #size-cells = <0>;
  524. };
  525.  
  526. i2c1: i2c@5002400 {
  527. compatible = "allwinner,sun50i-h616-i2c",
  528. "allwinner,sun6i-a31-i2c";
  529. reg = <0x05002400 0x400>;
  530. interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  531. clocks = <&ccu CLK_BUS_I2C1>;
  532. resets = <&ccu RST_BUS_I2C1>;
  533. status = "disabled";
  534. #address-cells = <1>;
  535. #size-cells = <0>;
  536. };
  537.  
  538. i2c2: i2c@5002800 {
  539. compatible = "allwinner,sun50i-h616-i2c",
  540. "allwinner,sun6i-a31-i2c";
  541. reg = <0x05002800 0x400>;
  542. interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  543. clocks = <&ccu CLK_BUS_I2C2>;
  544. resets = <&ccu RST_BUS_I2C2>;
  545. status = "disabled";
  546. #address-cells = <1>;
  547. #size-cells = <0>;
  548. };
  549.  
  550. i2c3: i2c@5002c00 {
  551. compatible = "allwinner,sun50i-h616-i2c",
  552. "allwinner,sun6i-a31-i2c";
  553. reg = <0x05002c00 0x400>;
  554. interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
  555. clocks = <&ccu CLK_BUS_I2C3>;
  556. resets = <&ccu RST_BUS_I2C3>;
  557. status = "disabled";
  558. #address-cells = <1>;
  559. #size-cells = <0>;
  560. };
  561.  
  562. i2c4: i2c@5003000 {
  563. compatible = "allwinner,sun50i-h616-i2c",
  564. "allwinner,sun6i-a31-i2c";
  565. reg = <0x05003000 0x400>;
  566. interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
  567. clocks = <&ccu CLK_BUS_I2C4>;
  568. resets = <&ccu RST_BUS_I2C4>;
  569. status = "disabled";
  570. #address-cells = <1>;
  571. #size-cells = <0>;
  572. };
  573.  
  574. spi0: spi@5010000 {
  575. compatible = "allwinner,sun50i-h616-spi",
  576. "allwinner,sun8i-h3-spi";
  577. reg = <0x05010000 0x1000>;
  578. interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
  579. clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
  580. clock-names = "ahb", "mod";
  581. resets = <&ccu RST_BUS_SPI0>;
  582. pinctrl-names = "default";
  583. pinctrl-0 = <&spi0_pins>;
  584. status = "disabled";
  585. #address-cells = <1>;
  586. #size-cells = <0>;
  587. };
  588.  
  589. spi1: spi@5011000 {
  590. compatible = "allwinner,sun50i-h616-spi",
  591. "allwinner,sun8i-h3-spi";
  592. reg = <0x05011000 0x1000>;
  593. interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
  594. clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
  595. clock-names = "ahb", "mod";
  596. resets = <&ccu RST_BUS_SPI1>;
  597. pinctrl-names = "default";
  598. pinctrl-0 = <&spi1_pins>;
  599. status = "disabled";
  600. #address-cells = <1>;
  601. #size-cells = <0>;
  602. };
  603.  
  604. emac0: ethernet@5020000 {
  605. compatible = "allwinner,sun50i-h616-emac",
  606. "allwinner,sun50i-a64-emac";
  607. syscon = <&syscon>;
  608. reg = <0x05020000 0x10000>;
  609. interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
  610. interrupt-names = "macirq";
  611. resets = <&ccu RST_BUS_EMAC0>;
  612. reset-names = "stmmaceth";
  613. clocks = <&ccu CLK_BUS_EMAC0>;
  614. clock-names = "stmmaceth";
  615. status = "disabled";
  616.  
  617. mdio0: mdio {
  618. compatible = "snps,dwmac-mdio";
  619. #address-cells = <1>;
  620. #size-cells = <0>;
  621. };
  622. };
  623.  
  624. emac1: ethernet@5030000 {
  625. compatible = "allwinner,sun50i-h616-emac";
  626. syscon = <&syscon 1>;
  627. reg = <0x05030000 0x10000>;
  628. interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
  629. interrupt-names = "macirq";
  630. resets = <&ccu RST_BUS_EMAC1>;
  631. reset-names = "stmmaceth";
  632. clocks = <&ccu CLK_BUS_EMAC1>;
  633. clock-names = "stmmaceth";
  634. status = "disabled";
  635.  
  636. mdio1: mdio {
  637. compatible = "snps,dwmac-mdio";
  638. #address-cells = <1>;
  639. #size-cells = <0>;
  640. };
  641. };
  642.  
  643. usbotg: usb@5100000 {
  644. compatible = "allwinner,sun50i-h616-musb",
  645. "allwinner,sun8i-h3-musb";
  646. reg = <0x05100000 0x0400>;
  647. clocks = <&ccu CLK_BUS_OTG>;
  648. resets = <&ccu RST_BUS_OTG>;
  649. interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  650. interrupt-names = "mc";
  651. phys = <&usbphy 0>;
  652. phy-names = "usb";
  653. extcon = <&usbphy 0>;
  654. status = "disabled";
  655. };
  656.  
  657. usbphy: phy@5100400 {
  658. compatible = "allwinner,sun50i-h616-usb-phy";
  659. reg = <0x05100400 0x24>,
  660. <0x05101800 0x14>,
  661. <0x05200800 0x14>,
  662. <0x05310800 0x14>,
  663. <0x05311800 0x14>;
  664. reg-names = "phy_ctrl",
  665. "pmu0",
  666. "pmu1",
  667. "pmu2",
  668. "pmu3";
  669. clocks = <&ccu CLK_USB_PHY0>,
  670. <&ccu CLK_USB_PHY1>,
  671. <&ccu CLK_USB_PHY2>,
  672. <&ccu CLK_USB_PHY3>;
  673. clock-names = "usb0_phy",
  674. "usb1_phy",
  675. "usb2_phy",
  676. "usb3_phy";
  677. resets = <&ccu RST_USB_PHY0>,
  678. <&ccu RST_USB_PHY1>,
  679. <&ccu RST_USB_PHY2>,
  680. <&ccu RST_USB_PHY3>;
  681. reset-names = "usb0_reset",
  682. "usb1_reset",
  683. "usb2_reset",
  684. "usb3_reset";
  685. status = "disabled";
  686. #phy-cells = <1>;
  687. };
  688.  
  689. ehci0: usb@5101000 {
  690. compatible = "allwinner,sun50i-h616-ehci",
  691. "generic-ehci";
  692. reg = <0x05101000 0x100>;
  693. interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
  694. clocks = <&ccu CLK_BUS_OHCI0>,
  695. <&ccu CLK_BUS_EHCI0>,
  696. <&ccu CLK_USB_OHCI0>;
  697. resets = <&ccu RST_BUS_OHCI0>,
  698. <&ccu RST_BUS_EHCI0>;
  699. phys = <&usbphy 0>;
  700. phy-names = "usb";
  701. status = "disabled";
  702. };
  703.  
  704. ohci0: usb@5101400 {
  705. compatible = "allwinner,sun50i-h616-ohci",
  706. "generic-ohci";
  707. reg = <0x05101400 0x100>;
  708. interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
  709. clocks = <&ccu CLK_BUS_OHCI0>,
  710. <&ccu CLK_USB_OHCI0>;
  711. resets = <&ccu RST_BUS_OHCI0>;
  712. phys = <&usbphy 0>;
  713. phy-names = "usb";
  714. status = "disabled";
  715. };
  716.  
  717. ehci1: usb@5200000 {
  718. compatible = "allwinner,sun50i-h616-ehci",
  719. "generic-ehci";
  720. reg = <0x05200000 0x100>;
  721. interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
  722. clocks = <&ccu CLK_BUS_OHCI1>,
  723. <&ccu CLK_BUS_EHCI1>,
  724. <&ccu CLK_USB_OHCI1>;
  725. resets = <&ccu RST_BUS_OHCI1>,
  726. <&ccu RST_BUS_EHCI1>;
  727. phys = <&usbphy 1>;
  728. phy-names = "usb";
  729. status = "disabled";
  730. };
  731.  
  732. ohci1: usb@5200400 {
  733. compatible = "allwinner,sun50i-h616-ohci",
  734. "generic-ohci";
  735. reg = <0x05200400 0x100>;
  736. interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
  737. clocks = <&ccu CLK_BUS_OHCI1>,
  738. <&ccu CLK_USB_OHCI1>;
  739. resets = <&ccu RST_BUS_OHCI1>;
  740. phys = <&usbphy 1>;
  741. phy-names = "usb";
  742. status = "disabled";
  743. };
  744.  
  745. ehci2: usb@5310000 {
  746. compatible = "allwinner,sun50i-h616-ehci",
  747. "generic-ehci";
  748. reg = <0x05310000 0x100>;
  749. interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  750. clocks = <&ccu CLK_BUS_OHCI2>,
  751. <&ccu CLK_BUS_EHCI2>,
  752. <&ccu CLK_USB_OHCI2>;
  753. resets = <&ccu RST_BUS_OHCI2>,
  754. <&ccu RST_BUS_EHCI2>;
  755. phys = <&usbphy 2>;
  756. phy-names = "usb";
  757. status = "disabled";
  758. };
  759.  
  760. ohci2: usb@5310400 {
  761. compatible = "allwinner,sun50i-h616-ohci",
  762. "generic-ohci";
  763. reg = <0x05310400 0x100>;
  764. interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
  765. clocks = <&ccu CLK_BUS_OHCI2>,
  766. <&ccu CLK_USB_OHCI2>;
  767. resets = <&ccu RST_BUS_OHCI2>;
  768. phys = <&usbphy 2>;
  769. phy-names = "usb";
  770. status = "disabled";
  771. };
  772.  
  773. ehci3: usb@5311000 {
  774. compatible = "allwinner,sun50i-h616-ehci",
  775. "generic-ehci";
  776. reg = <0x05311000 0x100>;
  777. interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  778. clocks = <&ccu CLK_BUS_OHCI3>,
  779. <&ccu CLK_BUS_EHCI3>,
  780. <&ccu CLK_USB_OHCI3>;
  781. resets = <&ccu RST_BUS_OHCI3>,
  782. <&ccu RST_BUS_EHCI3>;
  783. phys = <&usbphy 3>;
  784. phy-names = "usb";
  785. status = "disabled";
  786. };
  787.  
  788. ohci3: usb@5311400 {
  789. compatible = "allwinner,sun50i-h616-ohci",
  790. "generic-ohci";
  791. reg = <0x05311400 0x100>;
  792. interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
  793. clocks = <&ccu CLK_BUS_OHCI3>,
  794. <&ccu CLK_USB_OHCI3>;
  795. resets = <&ccu RST_BUS_OHCI3>;
  796. phys = <&usbphy 3>;
  797. phy-names = "usb";
  798. status = "disabled";
  799. };
  800.  
  801. hdmi: hdmi@6000000 {
  802. compatible = "allwinner,sun50i-h616-dw-hdmi",
  803. "allwinner,sun50i-h6-dw-hdmi";
  804. reg = <0x06000000 0x10000>;
  805. reg-io-width = <1>;
  806. interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
  807. clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
  808. <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
  809. <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
  810. clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
  811. "hdcp-bus";
  812. resets = <&ccu RST_BUS_HDMI>, <&ccu RST_BUS_HDCP>;
  813. reset-names = "ctrl", "hdcp";
  814. phys = <&hdmi_phy>;
  815. phy-names = "phy";
  816. status = "disabled";
  817.  
  818. ports {
  819. #address-cells = <1>;
  820. #size-cells = <0>;
  821.  
  822. hdmi_in: port@0 {
  823. reg = <0>;
  824.  
  825. hdmi_in_tcon_top: endpoint {
  826. remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
  827. };
  828. };
  829.  
  830. hdmi_out: port@1 {
  831. reg = <1>;
  832. };
  833. };
  834. };
  835.  
  836. hdmi_phy: hdmi-phy@6010000 {
  837. compatible = "allwinner,sun50i-h616-hdmi-phy";
  838. reg = <0x06010000 0x10000>;
  839. clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
  840. clock-names = "bus", "mod";
  841. resets = <&ccu RST_BUS_HDMI_SUB>;
  842. reset-names = "phy";
  843. #phy-cells = <0>;
  844. };
  845.  
  846. tcon_top: tcon-top@6510000 {
  847. compatible = "allwinner,sun50i-h6-tcon-top";
  848. reg = <0x06510000 0x1000>;
  849. clocks = <&ccu CLK_BUS_TCON_TOP>,
  850. <&ccu CLK_TCON_TV0>;
  851. clock-names = "bus",
  852. "tcon-tv0";
  853. clock-output-names = "tcon-top-tv0";
  854. resets = <&ccu RST_BUS_TCON_TOP>;
  855. #clock-cells = <1>;
  856.  
  857. ports {
  858. #address-cells = <1>;
  859. #size-cells = <0>;
  860.  
  861. tcon_top_mixer0_in: port@0 {
  862. #address-cells = <1>;
  863. #size-cells = <0>;
  864. reg = <0>;
  865.  
  866. tcon_top_mixer0_in_mixer0: endpoint@0 {
  867. reg = <0>;
  868. remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
  869. };
  870. };
  871.  
  872. tcon_top_mixer0_out: port@1 {
  873. #address-cells = <1>;
  874. #size-cells = <0>;
  875. reg = <1>;
  876.  
  877. tcon_top_mixer0_out_tcon_tv: endpoint@2 {
  878. reg = <2>;
  879. remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>;
  880. };
  881. };
  882.  
  883. tcon_top_hdmi_in: port@4 {
  884. #address-cells = <1>;
  885. #size-cells = <0>;
  886. reg = <4>;
  887.  
  888. tcon_top_hdmi_in_tcon_tv: endpoint@0 {
  889. reg = <0>;
  890. remote-endpoint = <&tcon_tv_out_tcon_top>;
  891. };
  892. };
  893.  
  894. tcon_top_hdmi_out: port@5 {
  895. reg = <5>;
  896.  
  897. tcon_top_hdmi_out_hdmi: endpoint {
  898. remote-endpoint = <&hdmi_in_tcon_top>;
  899. };
  900. };
  901. };
  902. };
  903.  
  904. video-codec@1c0e000 {
  905. compatible = "allwinner,sun50i-h6-video-engine";
  906. reg = <0x01c0e000 0x2000>;
  907. clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
  908. <&ccu CLK_MBUS_VE>;
  909. clock-names = "ahb", "mod", "ram";
  910. resets = <&ccu RST_BUS_VE>;
  911. interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
  912. allwinner,sram = <&ve_sram 1>;
  913. iommus = <&iommu 3>;
  914. };
  915.  
  916. gpu: gpu@0x01800000 {
  917. compatible = "allwinner,sun50i-h616-mali", "arm,mali-bifrost";
  918. reg = <0x1800000 0x40000>;
  919. interrupt-parent = <&gic>;
  920. interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
  921. <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
  922. <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
  923. interrupt-names = "job", "mmu", "gpu";
  924. clocks = <&ccu CLK_GPU0>, <&ccu CLK_BUS_GPU>;
  925. clock-names = "core", "bus";
  926. resets = <&ccu RST_BUS_GPU>;
  927. operating-points-v2 = <&gpu_opp_table>;
  928. #cooling-cells = <2>;
  929. status = "disabled";
  930. };
  931.  
  932. tcon_tv: lcd-controller@6515000 {
  933. compatible = "allwinner,sun50i-h6-tcon-tv",
  934. "allwinner,sun8i-r40-tcon-tv";
  935. reg = <0x06515000 0x1000>;
  936. interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
  937. clocks = <&ccu CLK_BUS_TCON_TV0>,
  938. <&tcon_top CLK_TCON_TOP_TV0>;
  939. clock-names = "ahb",
  940. "tcon-ch1";
  941. resets = <&ccu RST_BUS_TCON_TV0>;
  942. reset-names = "lcd";
  943.  
  944. ports {
  945. #address-cells = <1>;
  946. #size-cells = <0>;
  947.  
  948. tcon_tv_in: port@0 {
  949. reg = <0>;
  950.  
  951. tcon_tv_in_tcon_top_mixer0: endpoint {
  952. remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>;
  953. };
  954. };
  955.  
  956. tcon_tv_out: port@1 {
  957. #address-cells = <1>;
  958. #size-cells = <0>;
  959. reg = <1>;
  960.  
  961. tcon_tv_out_tcon_top: endpoint@1 {
  962. reg = <1>;
  963. remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>;
  964. };
  965. };
  966. };
  967. };
  968.  
  969. rtc: rtc@7000000 {
  970. compatible = "allwinner,sun50i-h616-rtc",
  971. "allwinner,sun50i-h6-rtc";
  972. reg = <0x07000000 0x400>;
  973. interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
  974. <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
  975. clock-output-names = "osc32k", "osc32k-out", "iosc";
  976. #clock-cells = <1>;
  977. };
  978.  
  979. r_ccu: clock@7010000 {
  980. compatible = "allwinner,sun50i-h616-r-ccu";
  981. reg = <0x07010000 0x210>;
  982. clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
  983. <&ccu CLK_PLL_PERIPH0>;
  984. clock-names = "hosc", "losc", "iosc", "pll-periph";
  985. #clock-cells = <1>;
  986. #reset-cells = <1>;
  987. };
  988.  
  989. r_pio: pinctrl@7022000 {
  990. compatible = "allwinner,sun50i-h616-r-pinctrl";
  991. reg = <0x07022000 0x400>;
  992. interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
  993. clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>;
  994. clock-names = "apb", "hosc", "losc";
  995. gpio-controller;
  996. #gpio-cells = <3>;
  997. interrupt-controller;
  998. #interrupt-cells = <3>;
  999.  
  1000. r_i2c_pins: r-i2c-pins {
  1001. pins = "PL0", "PL1";
  1002. function = "s_i2c";
  1003. };
  1004.  
  1005. r_rsb_pins: r-rsb-pins {
  1006. pins = "PL0", "PL1";
  1007. function = "s_rsb";
  1008. };
  1009. };
  1010.  
  1011. ir: ir@7040000 {
  1012. compatible = "allwinner,sun50i-h616-ir",
  1013. "allwinner,sun6i-a31-ir";
  1014. reg = <0x07040000 0x400>;
  1015. interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
  1016. clocks = <&r_ccu CLK_R_APB1_IR>,
  1017. <&r_ccu CLK_IR>;
  1018. clock-names = "apb", "ir";
  1019. resets = <&r_ccu RST_R_APB1_IR>;
  1020. pinctrl-names = "default";
  1021. pinctrl-0 = <&ir_rx_pin>;
  1022. status = "disabled";
  1023. };
  1024.  
  1025. r_i2c: i2c@7081400 {
  1026. compatible = "allwinner,sun50i-h616-i2c",
  1027. "allwinner,sun6i-a31-i2c";
  1028. reg = <0x07081400 0x400>;
  1029. interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
  1030. clocks = <&r_ccu CLK_R_APB2_I2C>;
  1031. resets = <&r_ccu RST_R_APB2_I2C>;
  1032. status = "disabled";
  1033. #address-cells = <1>;
  1034. #size-cells = <0>;
  1035. };
  1036.  
  1037. r_rsb: rsb@7083000 {
  1038. compatible = "allwinner,sun50i-h616-rsb",
  1039. "allwinner,sun8i-a23-rsb";
  1040. reg = <0x07083000 0x400>;
  1041. interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
  1042. clocks = <&r_ccu CLK_R_APB2_RSB>;
  1043. clock-frequency = <3000000>;
  1044. resets = <&r_ccu RST_R_APB2_RSB>;
  1045. pinctrl-names = "default";
  1046. pinctrl-0 = <&r_rsb_pins>;
  1047. status = "disabled";
  1048. #address-cells = <1>;
  1049. #size-cells = <0>;
  1050. };
  1051.  
  1052. ths: thermal-sensor@5070400 {
  1053. /* The Thermal Sensor Controller(THS) embeds four thermal sensors,
  1054. sensor0 is located in GPU
  1055. sensor1 is located in VE
  1056. sensor2 is located in CPU
  1057. sensor3 is located in DDR
  1058. */
  1059. compatible = "allwinner,sun50i-h616-ths";
  1060. reg = <0x05070400 0x400>;
  1061. interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
  1062. clocks = <&ccu CLK_BUS_THS>;
  1063. clock-names = "bus";
  1064. resets = <&ccu RST_BUS_THS>;
  1065. nvmem-cells = <&ths_calibration>;
  1066. nvmem-cell-names = "calibration";
  1067. #thermal-sensor-cells = <1>;
  1068. };
  1069. };
  1070.  
  1071. thermal-zones {
  1072. cpu-thermal {
  1073. polling-delay-passive = <0>;
  1074. polling-delay = <0>;
  1075. thermal-sensors = <&ths 2>;
  1076.  
  1077. trips {
  1078. cpu_alert: cpu-alert {
  1079. temperature = <85000>;
  1080. hysteresis = <2000>;
  1081. type = "passive";
  1082. };
  1083.  
  1084. cpu-crit {
  1085. temperature = <100000>;
  1086. hysteresis = <0>;
  1087. type = "critical";
  1088. };
  1089. };
  1090.  
  1091. cooling-maps {
  1092. map0 {
  1093. trip = <&cpu_alert>;
  1094. cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  1095. <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  1096. <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  1097. <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  1098. };
  1099. };
  1100. };
  1101.  
  1102. gpu-thermal {
  1103. polling-delay-passive = <0>;
  1104. polling-delay = <0>;
  1105. thermal-sensors = <&ths 0>;
  1106.  
  1107. trips {
  1108. gpu_alert: gpu-alert {
  1109. temperature = <85000>;
  1110. hysteresis = <2000>;
  1111. type = "passive";
  1112. };
  1113.  
  1114. gpu-crit {
  1115. temperature = <100000>;
  1116. hysteresis = <0>;
  1117. type = "critical";
  1118. };
  1119. };
  1120.  
  1121. cooling-maps {
  1122. map0 {
  1123. trip = <&gpu_alert>;
  1124. cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  1125. };
  1126. };
  1127. };
  1128.  
  1129. ve-thermal {
  1130. polling-delay-passive = <0>;
  1131. polling-delay = <0>;
  1132. thermal-sensors = <&ths 1>;
  1133. };
  1134.  
  1135. ddr-thermal {
  1136. polling-delay-passive = <0>;
  1137. polling-delay = <0>;
  1138. thermal-sensors = <&ths 3>;
  1139. };
  1140. };
  1141.  
  1142. cpu_opp_table: cpu-opp-table {
  1143. compatible = "allwinner,sun50i-h616-operating-points";
  1144. nvmem-cells = <&cpu_speed_grade>;
  1145. opp-shared;
  1146.  
  1147. opp-480000000 {
  1148. clock-latency-ns = <244144>; /* 8 32k periods */
  1149. opp-hz = /bits/ 64 <480000000>;
  1150.  
  1151. opp-microvolt-speed0 = <820000 820000 1120000>;
  1152. opp-microvolt-speed1 = <880000 880000 1120000>;
  1153. opp-microvolt-speed2 = <880000 880000 1120000>;
  1154. };
  1155.  
  1156. opp-600000000 {
  1157. clock-latency-ns = <244144>; /* 8 32k periods */
  1158. opp-hz = /bits/ 64 <600000000>;
  1159.  
  1160. opp-microvolt-speed0 = <820000 820000 1120000>;
  1161. opp-microvolt-speed1 = <880000 880000 1120000>;
  1162. opp-microvolt-speed2 = <880000 880000 1120000>;
  1163. };
  1164.  
  1165. opp-792000000 {
  1166. clock-latency-ns = <244144>; /* 8 32k periods */
  1167. opp-hz = /bits/ 64 <792000000>;
  1168.  
  1169. opp-microvolt-speed0 = <860000 860000 1120000>;
  1170. opp-microvolt-speed1 = <940000 940000 1120000>;
  1171. opp-microvolt-speed2 = <940000 940000 1120000>;
  1172. };
  1173.  
  1174. opp-1008000000 {
  1175. clock-latency-ns = <244144>; /* 8 32k periods */
  1176. opp-hz = /bits/ 64 <1008000000>;
  1177.  
  1178. opp-microvolt-speed0 = <900000 900000 1120000>;
  1179. opp-microvolt-speed1 = <1020000 1020000 1120000>;
  1180. opp-microvolt-speed2 = <1020000 1020000 1120000>;
  1181. };
  1182.  
  1183. opp-1200000000 {
  1184. clock-latency-ns = <244144>; /* 8 32k periods */
  1185. opp-hz = /bits/ 64 <1200000000>;
  1186.  
  1187. opp-microvolt-speed0 = <960000 960000 11200000>;
  1188. opp-microvolt-speed1 = <1100000 1100000 1120000>;
  1189. opp-microvolt-speed2 = <1100000 1100000 1120000>;
  1190. };
  1191.  
  1192. opp-1296000000 {
  1193. clock-latency-ns = <244144>; /* 8 32k periods */
  1194. opp-hz = /bits/ 64 <1296000000>;
  1195.  
  1196. opp-microvolt-speed0 = <1100000 1100000 1120000>;
  1197. opp-microvolt-speed1 = <1100000 1100000 1120000>;
  1198. opp-microvolt-speed2 = <1100000 1100000 1120000>;
  1199. };
  1200.  
  1201. opp-1344000000 {
  1202. clock-latency-ns = <244144>; /* 8 32k periods */
  1203. opp-hz = /bits/ 64 <1344000000>;
  1204.  
  1205. opp-microvolt-speed0 = <1120000 1120000 1120000>;
  1206. opp-microvolt-speed1 = <1120000 1120000 1120000>;
  1207. opp-microvolt-speed2 = <1120000 1120000 1120000>;
  1208. };
  1209.  
  1210. // opp-1512000000 {
  1211. // clock-latency-ns = <244144>; /* 8 32k periods */
  1212. // opp-hz = /bits/ 64 <1512000000>;
  1213.  
  1214. // opp-microvolt-speed0 = <1160000 1160000 1160000>;
  1215. // opp-microvolt-speed1 = <1160000 1160000 1160000>;
  1216. // opp-microvolt-speed2 = <1160000 1160000 1160000>;
  1217. // };
  1218. };
  1219.  
  1220. gpu_opp_table: gpu-opp-table {
  1221. compatible = "operating-points-v2";
  1222. opp-125000000 {
  1223. opp-hz = /bits/ 64 <125000000>;
  1224. opp-microvolt = <810000>;
  1225. };
  1226. opp-250000000 {
  1227. opp-hz = /bits/ 64 <250000000>;
  1228. opp-microvolt = <810000>;
  1229. };
  1230. opp-432000000 {
  1231. opp-hz = /bits/ 64 <432000000>;
  1232. opp-microvolt = <810000>;
  1233. };
  1234. opp-600000000 {
  1235. opp-hz = /bits/ 64 <600000000>;
  1236. opp-microvolt = <960000>;
  1237. };
  1238. opp-800000000 {
  1239. opp-hz = /bits/ 64 <800000000>;
  1240. opp-microvolt = <1080000>;
  1241. };
  1242. };
  1243. };
  1244.  
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement
Public Pastes
Advertisement
We use cookies for various purposes including analytics. By continuing to use Pastebin, you agree to our use of cookies as described in the Cookies Policy.  OK, I Understand
Not a member of Pastebin yet?
Sign Up, it unlocks many cool features!