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  1. #cpudef "CPU_65C02_CS_ALT"
  2. {
  3. #bits 8
  4.  
  5. ;------------------------------------------------------------------------------ (++ means new Instruction, +* means new Addressing Mode)
  6. ; Add with Carry
  7. ADC #{src} -> 0x69[7:0] @ src[7:0]
  8. ADC {src} -> {assert({src} <= 0xFF), 0x65[7:0] @ src[7:0]}
  9. ADC {src},X -> {assert({src} <= 0xFF), 0x75[7:0] @ src[7:0]}
  10. ADC {src} -> {assert({src} > 0xFF), 0x6D[7:0] @ src[7:0] @ src[15:8]}
  11. ADC {src},X -> {assert({src} > 0xFF), 0x7D[7:0] @ src[7:0] @ src[15:8]}
  12. ADC {src},Y -> {assert({src} > 0xFF), 0x79[7:0] @ src[7:0] @ src[15:8]}
  13. ADC ({src},X) -> 0x61[7:0] @ src[7:0]
  14. ADC ({src}),Y -> 0x71[7:0] @ src[7:0]
  15. ADC ({src}) -> 0x72[7:0] @ src[7:0] ; +*
  16.  
  17. ;------------------------------------------------------------------------------
  18. ; Logic AND
  19. AND #{src} -> 0x29[7:0] @ src[7:0]
  20. AND {src} -> {assert({src} <= 0xFF), 0x25[7:0] @ src[7:0]}
  21. AND {src},X -> {assert({src} <= 0xFF), 0x35[7:0] @ src[7:0]}
  22. AND {src} -> {assert({src} > 0xFF), 0x2D[7:0] @ src[7:0] @ src[15:8]}
  23. AND {src},X -> {assert({src} > 0xFF), 0x3D[7:0] @ src[7:0] @ src[15:8]}
  24. AND {src},Y -> {assert({src} > 0xFF), 0x39[7:0] @ src[7:0] @ src[15:8]}
  25. AND ({src},X) -> 0x21[7:0] @ src[7:0]
  26. AND ({src}),Y -> 0x31[7:0] @ src[7:0]
  27. AND ({src}) -> 0x32[7:0] @ src[7:0] ; +*
  28.  
  29. ;------------------------------------------------------------------------------
  30. ; Shift Left
  31. SFL A -> 0x0A[7:0]
  32. SFL {src} -> {assert({src} <= 0xFF), 0x06[7:0] @ src[7:0]}
  33. SFL {src},X -> {assert({src} <= 0xFF), 0x16[7:0] @ src[7:0]}
  34. SFL {src} -> {assert({src} > 0xFF), 0x0E[7:0] @ src[7:0] @ src[15:8]}
  35. SFL {src},X -> {assert({src} > 0xFF), 0x1E[7:0] @ src[7:0] @ src[15:8]}
  36.  
  37. ;------------------------------------------------------------------------------
  38. ; Branch Always ++
  39. BRA {src} -> 0x80[7:0] @ (src - (pc + 2))[7:0]
  40.  
  41. ;------------------------------------------------------------------------------
  42. ; Branch on Bit Clear ++
  43. BBC0 {src},{src1} -> 0x0F[7:0] @ src[7:0] @ ({src1} - (pc + 3))[7:0]
  44. BBC1 {src},{src1} -> 0x1F[7:0] @ src[7:0] @ ({src1} - (pc + 3))[7:0]
  45. BBC2 {src},{src1} -> 0x2F[7:0] @ src[7:0] @ ({src1} - (pc + 3))[7:0]
  46. BBC3 {src},{src1} -> 0x3F[7:0] @ src[7:0] @ ({src1} - (pc + 3))[7:0]
  47. BBC4 {src},{src1} -> 0x4F[7:0] @ src[7:0] @ ({src1} - (pc + 3))[7:0]
  48. BBC5 {src},{src1} -> 0x5F[7:0] @ src[7:0] @ ({src1} - (pc + 3))[7:0]
  49. BBC6 {src},{src1} -> 0x6F[7:0] @ src[7:0] @ ({src1} - (pc + 3))[7:0]
  50. BBC7 {src},{src1} -> 0x7F[7:0] @ src[7:0] @ ({src1} - (pc + 3))[7:0]
  51.  
  52. BBC {val},{src},{src1} -> {val}[3:0] @ 0xF[3:0] @ src[7:0] @ ({src1} - (pc + 3))[7:0]
  53.  
  54. BBR0 {src},{src1} -> 0x0F[7:0] @ src[7:0] @ ({src1} - (pc + 3))[7:0]
  55. BBR1 {src},{src1} -> 0x1F[7:0] @ src[7:0] @ ({src1} - (pc + 3))[7:0]
  56. BBR2 {src},{src1} -> 0x2F[7:0] @ src[7:0] @ ({src1} - (pc + 3))[7:0]
  57. BBR3 {src},{src1} -> 0x3F[7:0] @ src[7:0] @ ({src1} - (pc + 3))[7:0]
  58. BBR4 {src},{src1} -> 0x4F[7:0] @ src[7:0] @ ({src1} - (pc + 3))[7:0]
  59. BBR5 {src},{src1} -> 0x5F[7:0] @ src[7:0] @ ({src1} - (pc + 3))[7:0]
  60. BBR6 {src},{src1} -> 0x6F[7:0] @ src[7:0] @ ({src1} - (pc + 3))[7:0]
  61. BBR7 {src},{src1} -> 0x7F[7:0] @ src[7:0] @ ({src1} - (pc + 3))[7:0]
  62.  
  63. BBR {val},{src},{src1} -> {val}[3:0] @ 0xF[3:0] @ src[7:0] @ ({src1} - (pc + 3))[7:0]
  64.  
  65. ;------------------------------------------------------------------------------
  66. ; Branch on Bit Set ++
  67. BBS0 {src},{src1} -> 0x8F[7:0] @ src[7:0] @ ({src1} - (pc + 3))[7:0]
  68. BBS1 {src},{src1} -> 0x9F[7:0] @ src[7:0] @ ({src1} - (pc + 3))[7:0]
  69. BBS2 {src},{src1} -> 0xAF[7:0] @ src[7:0] @ ({src1} - (pc + 3))[7:0]
  70. BBS3 {src},{src1} -> 0xBF[7:0] @ src[7:0] @ ({src1} - (pc + 3))[7:0]
  71. BBS4 {src},{src1} -> 0xCF[7:0] @ src[7:0] @ ({src1} - (pc + 3))[7:0]
  72. BBS5 {src},{src1} -> 0xDF[7:0] @ src[7:0] @ ({src1} - (pc + 3))[7:0]
  73. BBS6 {src},{src1} -> 0xEF[7:0] @ src[7:0] @ ({src1} - (pc + 3))[7:0]
  74. BBS7 {src},{src1} -> 0xFF[7:0] @ src[7:0] @ ({src1} - (pc + 3))[7:0]
  75.  
  76. BBS {val},{src},{src1} -> ({val} + 8)[3:0] @ 0xF[3:0] @ src[7:0] @ ({src1} - (pc + 3))[7:0]
  77.  
  78. ;------------------------------------------------------------------------------
  79. ; Branch on Carry Clear
  80. BCC {src} -> 0x90[7:0] @ (src - (pc + 2))[7:0]
  81.  
  82. ;------------------------------------------------------------------------------
  83. ; Branch on Carry Set
  84. BCS {src} -> 0xB0[7:0] @ (src - (pc + 2))[7:0]
  85.  
  86. ;------------------------------------------------------------------------------
  87. ; Branch on Zero Set
  88. BZS {src} -> 0xF0[7:0] @ (src - (pc + 2))[7:0]
  89. BEQ {src} -> 0xF0[7:0] @ (src - (pc + 2))[7:0]
  90.  
  91. ;------------------------------------------------------------------------------
  92. ; Bit Test
  93. BIT #{src} -> 0x89[7:0] @ src[7:0] ; +*
  94. BIT {src} -> {assert({src} <= 0xFF), 0x24[7:0] @ src[7:0]}
  95. BIT {src},X -> {assert({src} <= 0xFF), 0x34[7:0] @ src[7:0]} ; +*
  96. BIT {src} -> {assert({src} > 0xFF), 0x2C[7:0] @ src[7:0] @ src[15:8]}
  97. BIT {src},X -> {assert({src} > 0xFF), 0x3C[7:0] @ src[7:0] @ src[15:8]} ; +*
  98.  
  99. ;------------------------------------------------------------------------------
  100. ; Branch Negative Set
  101. BNS {src} -> 0x30[7:0] @ (src - (pc + 2))[7:0]
  102. BMI {src} -> 0x30[7:0] @ (src - (pc + 2))[7:0]
  103.  
  104. ;------------------------------------------------------------------------------
  105. ; Branch on Zero Clear
  106. BZC {src} -> 0xD0[7:0] @ (src - (pc + 2))[7:0]
  107. BNE {src} -> 0xD0[7:0] @ (src - (pc + 2))[7:0]
  108.  
  109. ;------------------------------------------------------------------------------
  110. ; Branch Negative Clear
  111. BNC {src} -> 0x10[7:0] @ (src - (pc + 2))[7:0]
  112. BPL {src} -> 0x10[7:0] @ (src - (pc + 2))[7:0]
  113.  
  114. ;------------------------------------------------------------------------------
  115. ; Break (Interrupt)
  116. BRK -> 0x00[7:0]
  117.  
  118. ;------------------------------------------------------------------------------
  119. ; Branch on Overflow Clear
  120. BVC {src} -> 0x50[7:0] @ (src - (pc + 2))[7:0]
  121.  
  122. ;------------------------------------------------------------------------------
  123. ; Branch on Overflow Set
  124. BVS {src} -> 0x70[7:0] @ (src - (pc + 2))[7:0]
  125.  
  126. ;------------------------------------------------------------------------------
  127. ; Clear Carry
  128. CLC -> 0x18[7:0]
  129.  
  130. ;------------------------------------------------------------------------------
  131. ; Clear Decimal
  132. CLD -> 0xD8[7:0]
  133.  
  134. ;------------------------------------------------------------------------------
  135. ; Clear Interrupt Disable
  136. CLI -> 0x58[7:0]
  137.  
  138. ;------------------------------------------------------------------------------
  139. ; Clear Overflow
  140. CLV -> 0xB8[7:0]
  141.  
  142. ;------------------------------------------------------------------------------
  143. ; Compare with Accumulator
  144. CMP #{src} -> 0xC9[7:0] @ src[7:0]
  145. CMP {src} -> {assert({src} <= 0xFF), 0xC5[7:0] @ src[7:0]}
  146. CMP {src},X -> {assert({src} <= 0xFF), 0xD5[7:0] @ src[7:0]}
  147. CMP {src} -> {assert({src} > 0xFF), 0xCD[7:0] @ src[7:0] @ src[15:8]}
  148. CMP {src},X -> {assert({src} > 0xFF), 0xDD[7:0] @ src[7:0] @ src[15:8]}
  149. CMP {src},Y -> {assert({src} > 0xFF), 0xD9[7:0] @ src[7:0] @ src[15:8]}
  150. CMP ({src},X) -> 0xC1[7:0] @ src[7:0]
  151. CMP ({src}),Y -> 0xD1[7:0] @ src[7:0]
  152. CMP ({src}) -> 0xD2[7:0] @ src[7:0] ; +*
  153.  
  154. ;------------------------------------------------------------------------------
  155. ; Compare with X
  156. CPX #{src} -> 0xE0[7:0] @ src[7:0]
  157. CPX {src} -> {assert({src} <= 0xFF), 0xE4[7:0] @ src[7:0]}
  158. CPX {src} -> {assert({src} > 0xFF), 0xEC[7:0] @ src[7:0] @ src[15:8]}
  159.  
  160. ;------------------------------------------------------------------------------
  161. ; Compare with Y
  162. CPY #{src} -> 0xC0[7:0] @ src[7:0]
  163. CPY {src} -> {assert({src} <= 0xFF), 0xC4[7:0] @ src[7:0]}
  164. CPY {src} -> {assert({src} > 0xFF), 0xCC[7:0] @ src[7:0] @ src[15:8]}
  165.  
  166. ;------------------------------------------------------------------------------
  167. ; Decrement
  168. DEC A -> 0x1A[7:0] ; +*
  169. DEA -> 0x1A[7:0] ; +*
  170. DEC {src} -> {assert({src} <= 0xFF), 0xC6[7:0] @ src[7:0]}
  171. DEC {src},X -> {assert({src} <= 0xFF), 0xD6[7:0] @ src[7:0]}
  172. DEC {src} -> {assert({src} > 0xFF), 0xCE[7:0] @ src[7:0] @ src[15:8]}
  173. DEC {src},X -> {assert({src} > 0xFF), 0xDE[7:0] @ src[7:0] @ src[15:8]}
  174.  
  175. ;------------------------------------------------------------------------------
  176. ; Decrement X
  177. DEX -> 0xCA[7:0]
  178.  
  179. ;------------------------------------------------------------------------------
  180. ; Decrement Y
  181. DEY -> 0x88[7:0]
  182.  
  183. ;------------------------------------------------------------------------------
  184. ; Logic XOR
  185. XOR #{src} -> 0x49[7:0] @ src[7:0]
  186. XOR {src} -> {assert({src} <= 0xFF), 0x45[7:0] @ src[7:0]}
  187. XOR {src},X -> {assert({src} <= 0xFF), 0x55[7:0] @ src[7:0]}
  188. XOR {src} -> {assert({src} > 0xFF), 0x4D[7:0] @ src[7:0] @ src[15:8]}
  189. XOR {src},X -> {assert({src} > 0xFF), 0x5D[7:0] @ src[7:0] @ src[15:8]}
  190. XOR {src},Y -> {assert({src} > 0xFF), 0x59[7:0] @ src[7:0] @ src[15:8]}
  191. XOR ({src},X) -> 0x41[7:0] @ src[7:0]
  192. XOR ({src}),Y -> 0x51[7:0] @ src[7:0]
  193. XOR ({src}) -> 0x52[7:0] @ src[7:0] ; +*
  194.  
  195. ;------------------------------------------------------------------------------
  196. ; Increment
  197. INC A -> 0x3A[7:0] ; +*
  198. INA -> 0x3A[7:0] ; +*
  199. INC {src} -> {assert({src} <= 0xFF), 0xE6[7:0] @ src[7:0]}
  200. INC {src},X -> {assert({src} <= 0xFF), 0xF6[7:0] @ src[7:0]}
  201. INC {src} -> {assert({src} > 0xFF), 0xEE[7:0] @ src[7:0] @ src[15:8]}
  202. INC {src},X -> {assert({src} > 0xFF), 0xFE[7:0] @ src[7:0] @ src[15:8]}
  203.  
  204. ;------------------------------------------------------------------------------
  205. ; Increment X
  206. INX -> 0xE8[7:0]
  207.  
  208. ;------------------------------------------------------------------------------
  209. ; Increment Y
  210. INY -> 0xC8[7:0]
  211.  
  212. ;------------------------------------------------------------------------------
  213. ; Jump
  214. JMP {src} -> 0x4C[7:0] @ src[7:0] @ src[15:8]
  215. JMP ({src}) -> 0x6C[7:0] @ src[7:0] @ src[15:8]
  216. JMP ({src},X) -> 0x7C[7:0] @ src[7:0] @ src[15:8]
  217.  
  218. ;------------------------------------------------------------------------------
  219. ; Jump Subroutine
  220. JSR {src} -> 0x20[7:0] @ src[7:0] @ src[15:8]
  221.  
  222. ;------------------------------------------------------------------------------
  223. ; Load Accumulator
  224. LDA #{src} -> 0xA9[7:0] @ src[7:0]
  225. LDA {src} -> {assert({src} <= 0xFF), 0xA5[7:0] @ src[7:0]}
  226. LDA {src},X -> {assert({src} <= 0xFF), 0xB5[7:0] @ src[7:0]}
  227. LDA {src} -> {assert({src} > 0xFF), 0xAD[7:0] @ src[7:0] @ src[15:8]}
  228. LDA {src},X -> {assert({src} > 0xFF), 0xBD[7:0] @ src[7:0] @ src[15:8]}
  229. LDA {src},Y -> {assert({src} > 0xFF), 0xB9[7:0] @ src[7:0] @ src[15:8]}
  230. LDA ({src},X) -> 0xA1[7:0] @ src[7:0]
  231. LDA ({src}),Y -> 0xB1[7:0] @ src[7:0]
  232. LDA ({src}) -> 0xB2[7:0] @ src[7:0] ; +*
  233.  
  234. ;------------------------------------------------------------------------------
  235. ; Load X
  236. LDX #{src} -> 0xA2[7:0] @ src[7:0]
  237. LDX {src} -> {assert({src} <= 0xFF), 0xA6[7:0] @ src[7:0]}
  238. LDX {src},Y -> {assert({src} <= 0xFF), 0xB6[7:0] @ src[7:0]}
  239. LDX {src} -> {assert({src} > 0xFF), 0xAE[7:0] @ src[7:0] @ src[15:8]}
  240. LDX {src},Y -> {assert({src} > 0xFF), 0xBE[7:0] @ src[7:0] @ src[15:8]}
  241.  
  242. ;------------------------------------------------------------------------------
  243. ; Load Y
  244. LDY #{src} -> 0xA0[7:0] @ src[7:0]
  245. LDY {src} -> {assert({src} <= 0xFF), 0xA4[7:0] @ src[7:0]}
  246. LDY {src},X -> {assert({src} <= 0xFF), 0xB4[7:0] @ src[7:0]}
  247. LDY {src} -> {assert({src} > 0xFF), 0xAC[7:0] @ src[7:0] @ src[15:8]}
  248. LDY {src},X -> {assert({src} > 0xFF), 0xBC[7:0] @ src[7:0] @ src[15:8]}
  249.  
  250. ;------------------------------------------------------------------------------
  251. ; Logical Shift Right
  252. SFR A -> 0x4A[7:0]
  253. SFR {src} -> {assert({src} <= 0xFF), 0x46[7:0] @ src[7:0]}
  254. SFR {src},X -> {assert({src} <= 0xFF), 0x56[7:0] @ src[7:0]}
  255. SFR {src} -> {assert({src} > 0xFF), 0x4E[7:0] @ src[7:0] @ src[15:8]}
  256. SFR {src},X -> {assert({src} > 0xFF), 0x5E[7:0] @ src[7:0] @ src[15:8]}
  257.  
  258. ;------------------------------------------------------------------------------
  259. ; No Operation
  260. NOP -> 0xEA[7:0]
  261.  
  262. ;------------------------------------------------------------------------------
  263. ; Logic OR
  264. ORA #{src} -> 0x09[7:0] @ src[7:0]
  265. ORA {src} -> {assert({src} <= 0xFF), 0x06[7:0] @ src[7:0]}
  266. ORA {src},X -> {assert({src} <= 0xFF), 0x15[7:0] @ src[7:0]}
  267. ORA {src} -> {assert({src} > 0xFF), 0x0D[7:0] @ src[7:0] @ src[15:8]}
  268. ORA {src},X -> {assert({src} > 0xFF), 0x1D[7:0] @ src[7:0] @ src[15:8]}
  269. ORA {src},Y -> {assert({src} > 0xFF), 0x19[7:0] @ src[7:0] @ src[15:8]}
  270. ORA ({src},X) -> 0x01[7:0] @ src[7:0]
  271. ORA ({src}),Y -> 0x11[7:0] @ src[7:0]
  272. ORA ({src}) -> 0x12[7:0] @ src[7:0] ; +*
  273.  
  274. ;------------------------------------------------------------------------------
  275. ; Push Accumulator
  276. PHA -> 0x48[7:0]
  277.  
  278. ;------------------------------------------------------------------------------
  279. ; Push Processor Status
  280. PHP -> 0x08[7:0]
  281.  
  282. ;------------------------------------------------------------------------------
  283. ; Push X Register ++
  284. PHX -> 0xDA[7:0]
  285.  
  286. ;------------------------------------------------------------------------------
  287. ; Push Y Register ++
  288. PHY -> 0x5A[7:0]
  289.  
  290. ;------------------------------------------------------------------------------
  291. ; Pull Accumulator
  292. PLA -> 0x68[7:0]
  293.  
  294. ;------------------------------------------------------------------------------
  295. ; Pull Processor Status
  296. PLP -> 0x28[7:0]
  297.  
  298. ;------------------------------------------------------------------------------
  299. ; Pull X Register ++
  300. PLX -> 0xFA[7:0]
  301.  
  302. ;------------------------------------------------------------------------------
  303. ; Pull Y Register ++
  304. PLY -> 0x7A[7:0]
  305.  
  306. ;------------------------------------------------------------------------------
  307. ; Clear Memory Bit ++
  308. CMB0 {src} -> 0x07[7:0] @ src[7:0]
  309. CMB1 {src} -> 0x17[7:0] @ src[7:0]
  310. CMB2 {src} -> 0x27[7:0] @ src[7:0]
  311. CMB3 {src} -> 0x37[7:0] @ src[7:0]
  312. CMB4 {src} -> 0x47[7:0] @ src[7:0]
  313. CMB5 {src} -> 0x57[7:0] @ src[7:0]
  314. CMB6 {src} -> 0x67[7:0] @ src[7:0]
  315. CMB7 {src} -> 0x77[7:0] @ src[7:0]
  316.  
  317. CMB {val},{src} -> {val}[3:0] @ 0x7[3:0] @ src[7:0]
  318.  
  319. RMB0 {src} -> 0x07[7:0] @ src[7:0]
  320. RMB1 {src} -> 0x17[7:0] @ src[7:0]
  321. RMB2 {src} -> 0x27[7:0] @ src[7:0]
  322. RMB3 {src} -> 0x37[7:0] @ src[7:0]
  323. RMB4 {src} -> 0x47[7:0] @ src[7:0]
  324. RMB5 {src} -> 0x57[7:0] @ src[7:0]
  325. RMB6 {src} -> 0x67[7:0] @ src[7:0]
  326. RMB7 {src} -> 0x77[7:0] @ src[7:0]
  327.  
  328. RMB {val},{src} -> {val}[3:0] @ 0x7[3:0] @ src[7:0]
  329.  
  330. ;------------------------------------------------------------------------------
  331. ; Rotate Left
  332. ROL A -> 0x2A[7:0]
  333. ROL {src} -> {assert({src} <= 0xFF), 0x26[7:0] @ src[7:0]}
  334. ROL {src},X -> {assert({src} <= 0xFF), 0x36[7:0] @ src[7:0]}
  335. ROL {src} -> {assert({src} > 0xFF), 0x2E[7:0] @ src[7:0] @ src[15:8]}
  336. ROL {src},X -> {assert({src} > 0xFF), 0x3E[7:0] @ src[7:0] @ src[15:8]}
  337.  
  338. ;------------------------------------------------------------------------------
  339. ; Rotate Right
  340. ROR A -> 0x6A[7:0]
  341. ROR {src} -> {assert({src} <= 0xFF), 0x66[7:0] @ src[7:0]}
  342. ROR {src},X -> {assert({src} <= 0xFF), 0x76[7:0] @ src[7:0]}
  343. ROR {src} -> {assert({src} > 0xFF), 0x6E[7:0] @ src[7:0] @ src[15:8]}
  344. ROR {src},X -> {assert({src} > 0xFF), 0x7E[7:0] @ src[7:0] @ src[15:8]}
  345.  
  346. ;------------------------------------------------------------------------------
  347. ; Return from Interrupt
  348. RTI -> 0x40[7:0]
  349.  
  350. ;------------------------------------------------------------------------------
  351. ; Return from Subroutine
  352. RTS -> 0x60[7:0]
  353.  
  354. ;------------------------------------------------------------------------------
  355. ; Subtract with Carry
  356. SBC #{src} -> 0xE9[7:0] @ src[7:0]
  357. SBC {src} -> {assert({src} <= 0xFF), 0xE5[7:0] @ src[7:0]}
  358. SBC {src},X -> {assert({src} <= 0xFF), 0xF5[7:0] @ src[7:0]}
  359. SBC {src} -> {assert({src} > 0xFF), 0xED[7:0] @ src[7:0] @ src[15:8]}
  360. SBC {src},X -> {assert({src} > 0xFF), 0xFD[7:0] @ src[7:0] @ src[15:8]}
  361. SBC {src},Y -> {assert({src} > 0xFF), 0xF9[7:0] @ src[7:0] @ src[15:8]}
  362. SBC ({src},X) -> 0xE1[7:0] @ src[7:0]
  363. SBC ({src}),Y -> 0xF1[7:0] @ src[7:0]
  364. SBC ({src}) -> 0xF2[7:0] @ src[7:0] ; +*
  365.  
  366. ;------------------------------------------------------------------------------
  367. ; Set Carry
  368. SEC -> 0x38[7:0]
  369.  
  370. ;------------------------------------------------------------------------------
  371. ; Set Decimal
  372. SED -> 0xF8[7:0]
  373.  
  374. ;------------------------------------------------------------------------------
  375. ; Set Interrupt Disable
  376. SEI -> 0x78[7:0]
  377.  
  378. ;------------------------------------------------------------------------------
  379. ; Set Memory Bit ++
  380. SMB0 {src} -> 0x87[7:0] @ src[7:0]
  381. SMB1 {src} -> 0x97[7:0] @ src[7:0]
  382. SMB2 {src} -> 0xA7[7:0] @ src[7:0]
  383. SMB3 {src} -> 0xB7[7:0] @ src[7:0]
  384. SMB4 {src} -> 0xC7[7:0] @ src[7:0]
  385. SMB5 {src} -> 0xD7[7:0] @ src[7:0]
  386. SMB6 {src} -> 0xE7[7:0] @ src[7:0]
  387. SMB7 {src} -> 0xF7[7:0] @ src[7:0]
  388.  
  389. SMB {val},{src} -> ({val} + 8)[3:0] @ 0x7[3:0] @ src[7:0]
  390.  
  391. ;------------------------------------------------------------------------------
  392. ; Store Accumulator
  393. STA {src} -> {assert({src} <= 0xFF), 0x85[7:0] @ src[7:0]}
  394. STA {src},X -> {assert({src} <= 0xFF), 0x95[7:0] @ src[7:0]}
  395. STA {src} -> {assert({src} > 0xFF), 0x8D[7:0] @ src[7:0] @ src[15:8]}
  396. STA {src},X -> {assert({src} > 0xFF), 0x9D[7:0] @ src[7:0] @ src[15:8]}
  397. STA {src},Y -> {assert({src} > 0xFF), 0x99[7:0] @ src[7:0] @ src[15:8]}
  398. STA ({src},X) -> 0x81[7:0] @ src[7:0]
  399. STA ({src}),Y -> 0x91[7:0] @ src[7:0]
  400. STA ({src}) -> 0x92[7:0] @ src[7:0] ; +*
  401.  
  402. ;------------------------------------------------------------------------------
  403. ; Stop Processor (Halt) ++
  404. STP -> 0xDB[7:0]
  405. HLT -> 0xDB[7:0]
  406.  
  407. ;------------------------------------------------------------------------------
  408. ; Store X
  409. STX {src} -> {assert({src} <= 0xFF), 0x86[7:0] @ src[7:0]}
  410. STX {src},Y -> {assert({src} <= 0xFF), 0x96[7:0] @ src[7:0]}
  411. STX {src} -> {assert({src} > 0xFF), 0x8E[7:0] @ src[7:0] @ src[15:8]}
  412.  
  413. ;------------------------------------------------------------------------------
  414. ; Store Y
  415. STY {src} -> {assert({src} <= 0xFF), 0x84[7:0] @ src[7:0]}
  416. STY {src},X -> {assert({src} <= 0xFF), 0x94[7:0] @ src[7:0]}
  417. STY {src} -> {assert({src} > 0xFF), 0x8C[7:0] @ src[7:0] @ src[15:8]}
  418.  
  419. ;------------------------------------------------------------------------------
  420. ; Store Zero in Memory ++
  421. STZ {src} -> {assert({src} <= 0xFF), 0x64[7:0] @ src[7:0]}
  422. STZ {src},X -> {assert({src} <= 0xFF), 0x74[7:0] @ src[7:0]}
  423. STZ {src} -> {assert({src} > 0xFF), 0x9C[7:0] @ src[7:0] @ src[15:8]}
  424. STZ {src},X -> {assert({src} > 0xFF), 0x9E[7:0] @ src[7:0] @ src[15:8]}
  425.  
  426. ;------------------------------------------------------------------------------
  427. ; Transfer Accumulator to X
  428. TAX -> 0xAA[7:0]
  429.  
  430. ;------------------------------------------------------------------------------
  431. ; Transfer Accumulator to Y
  432. TAY -> 0xA8[7:0]
  433.  
  434. ;------------------------------------------------------------------------------
  435. ; Test and Clear memory bit ++
  436. TCB {src} -> {assert({src} <= 0xFF), 0x14[7:0] @ src[7:0]}
  437. TCB {src} -> {assert({src} > 0xFF), 0x1C[7:0] @ src[7:0] @ src[15:8]}
  438.  
  439. ;------------------------------------------------------------------------------
  440. ; Test and Set memory bit ++
  441. TSB {src} -> {assert({src} <= 0xFF), 0x04[7:0] @ src[7:0]}
  442. TSB {src} -> {assert({src} > 0xFF), 0x0C[7:0] @ src[7:0] @ src[15:8]}
  443.  
  444. ;------------------------------------------------------------------------------
  445. ; Transfer Stack Pointer to X
  446. TSX -> 0xBA[7:0]
  447.  
  448. ;------------------------------------------------------------------------------
  449. ; Transfer X to Accumulator
  450. TXA -> 0x8A[7:0]
  451.  
  452. ;------------------------------------------------------------------------------
  453. ; Transfer X to Stack Pointer
  454. TXS -> 0x9A[7:0]
  455.  
  456. ;------------------------------------------------------------------------------
  457. ; Transfer Y to Accumulator
  458. TYA -> 0x98[7:0]
  459. ;------------------------------------------------------------------------------
  460. ; Wait for Interrupt ++
  461. WAI -> 0xCB[7:0]
  462.  
  463. }
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