# Read libraries, design, enable power analysis
# and link design
set power_enable_analysis true
set link_library slow_pgpin.db
read_verilog power_pins.v
link
# Create back-up power nets
create_power_net_info vdd_backup -power
create_power_net_info vss_backup -gnd
# Create domain power nets
create_power_net_info t_vdd -power -switchable \
-nominal_voltages{1.2} -voltage_ranges{1.1 1.3}
create_power_net_info a_vdd -power
create_power_net_info b_vdd -power
# Create domain ground nets
create_power_net_info t_vss -gnd create_power_net_info a_vss -gnd
create_power_net_info b_vss -gnd
# Create internal power nets
create_power_net_info int_vdd_1 -power \
-nominal_voltages{1.2} -voltage_ranges[1.1 1.3} \ -switchable
create_power_net_info int_vdd_2 -power \  -nominal_voltages{1.25} -voltage_ranges{1.1 1.3}
create_power_net_info int_vdd_3 -power \ -nominal_voltages{1.2} -voltage_ranges{1.1 1.3}
create_power_net_info int_vdd_4 -power
# Create power domains create_power_domain t
create_power_domain a -object_list[get_cells PD0_inst]\ -power_down -power_down_ctrl[get_nets a] \ -power_down_ctrl_sense 0  create_power_domain b -object_list [get_cells PD1_inst]\ -power_down
# Connect rails to power domains  connect_power_domain t -primary_power_net t_vdd \
-primary_ground_net t_vss
connect_power_domain a -primary_power_net a_vdd \
-primary_ground_net a_vss \
-backup_power_net vdd_backup \
-backup_ground_net vss_backup
connect_power_domain b -primary_power_net b_vdd \ -primary_ground_net b_vss
# Set voltages of power nets
set_voltage 1.15 -object_list{t_vdd a_vdd b_vdd}
# Read SDC and other timing or power assertions
set_input_transition 0.0395 [all_inputs]
set_load 1.0 [all outputs]
# Perform timing analysis
update_timing
# Read switching activity
set_switching_activity...
set_switching_activity... ...
report_power