20141002_KUAS_Verilog_FullAdder_4Bit(DataFlow)

/***********************************************/
/** 20141002 4-Bit Full Adder (Use Data Flow) **/
/** Maker  : Yan                              **/
/** E-Mail : ssas1115577@gmail.com            **/
/** Date   : 2014/10/02 pm.10:45              **/
/***********************************************/

module FullAdder_4Bit(input1, input2, carryIn, sum, carryOut);
    input       [3:0]   input1, input2;
    input       carryIn;
    output      [3:0]   sum;
    output      carryOut;

    FullAdder_EightBit  #4  tmp1(.input1(input1), .input2(input2), .carryIn(carryIn), .sum(sum), .carryOut(carryOut));
endmodule

module FullAdder_EightBit(input1, input2, carryIn, sum, carryOut);
    parameter   BitLenght = 8;
    input       [BitLenght - 1 : 0] input1, input2;
    input       carryIn;
    output      [BitLenght - 1 : 0] sum;
    output      carryOut;

    assign  {carryOut, sum} = input1 + input2 + carryIn;
endmodule