`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:    12:56:50 11/14/2018
// Design Name:
// Module Name:    zad
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module zad #(parameter range=15)(input clk, rst, in,
                    output reg ready, ovl, output reg[clogb2(range)-1:0] data
    );

// detektor zbocza opadajacego
reg[1:0] tmp;
wire zbocze;

always @(posedge clk, posedge rst)
    if(rst)
        tmp <= 2'b00;
    else begin
        tmp[0] <= in;
        tmp[1] <= tmp[0];
    end

assign zbocze = ~tmp[0] & tmp[1];

reg[clogb2(range)-1:0] licznik;

// licznik
always @(posedge clk, posedge rst) begin
    if(rst) begin
        licznik <= 1'b0;
        ovl <= 1'b0;
    end
    else begin
        if (zbocze) begin
            licznik <= 1'b0;
        end
        else if (in) begin
            licznik <= licznik + 1'b1;
            if (licznik == range)
                ovl <= 1'b1;
        end
    end
end

// rejestr wyjsciowy
always @(posedge clk, posedge rst) begin
    if (rst) begin
        ready <= 1'b0;
        data <= 1'b0;
    end
    else if (zbocze) begin
            ready <= 1'b1;
            data <= licznik;
        end
        else begin
            ready <= 1'b0;
        end
end

// funkcja logarytmujaca
function integer clogb2(input integer value);
    begin
        value = value - 1;
        for(clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
            value = value >> 1;
    end
endfunction

endmodule