library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ram128x32 is
    Port ( address : in  STD_LOGIC_VECTOR(6 downto 0);
           rdata : out  STD_LOGIC_VECTOR(31 downto 0);
           wdata : in  STD_LOGIC_VECTOR(31 downto 0);
           wen : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           ce : in  STD_LOGIC;
           en : in  STD_LOGIC);
end ram128x32;

architecture Behavioral of ram128x32 is
	type ram_file_t is array (0 to 127) of std_logic_vector(31 downto 0);
	signal ram_file_s : ram_file_t := (others => (others => '0'));
begin
	ram: process (clk) is begin
		if rising_edge(clk) and ce = '1' then
			if reset = '1' then
				ram_file_s <= (others => (others => '0'));
			elsif en = '1' and wen = '1' then
				ram_file_s(conv_integer(address)) <= wdata;
			end if;
			rdata <= ram_file_s(conv_integer(address));
		end if;
	end process;
end Behavioral;