decod

module numarator(data, up_down, load, clk, reset, oe, result, tc);
input [3:0] data;
input up_down, load, clk, reset, oe;
output reg [3:0] result;
output reg tc;
always @(posedge clk) begin
 if(oe == 1) begin
  result = 4'bz;
  tc = 4'bz;
 end
 else begin
  if(reset == 1)
   result = 0;
  else begin
   if(load == 1)
    result = data;
   else begin
    if(up_down == 1) begin
     result = result + 1;
     if(result == 15)
      tc = 1;
     else
      tc = 0;
    end
    else begin
     result = result - 1;
     if(result == 0)
      tc = 1;
     else
      tc = 0;
    end
   end
  end
 end
end
endmodule

module tst_num();
reg [3:0] data;
reg up_down, load, clk, reset, oe;
wire [3:0] result;
wire tc;
initial begin
 clk = 1;
 forever
  #10 clk = ~clk;
end
initial begin
 oe = 1;
 #10 oe = 0; reset = 1;
 #20 reset = 0; load = 1; data = 11;
 #20 load = 0; up_down = 0;
 #200 up_down = 1;
 #150 reset = 1;
end
numarator tstn(data, up_down, load, clk, reset, oe, result, tc);
endmodule

module reg_deplasare(clk, rst, sd, s_in, d_in, datareg, q);
input clk, rst, s_in, d_in;
input [1:0] sd;
input [3:0] datareg;
output reg [3:0] q;
always @(posedge clk) begin
 if(rst == 1)
  q = 0;
 if(sd == 0)
  q = datareg;
 else if(sd == 1)
  q = {d_in, q[3:1]};
 else if(sd == 2)
  q = {q[2:0], s_in};
end
endmodule

module tst_reg();
reg clk, rst, s_in, d_in;
reg [1:0] sd;
reg [3:0] datareg;
wire [3:0] q;
initial begin
 clk = 1;
 forever
  #10 clk = ~clk;
end
initial begin
 sd = 0;
 datareg = 10;
 #10 d_in = 0; s_in = 1; sd = 2;
 #50 sd = 1;
end
reg_deplasare tstr(clk, rst, sd, s_in, d_in, datareg, q);
endmodule

module decodificator(in, oe, y);
input [3:0] in;
input oe;
output reg [15:0] y;
integer k;
always @(in or oe) begin
 if(oe == 1)
  y = 4'bz;
 else begin
  y = 0;
  for(k=0; k<=15; k=k+1)
   if(in == k)
    y[k] = 1;
 end
end
endmodule

module tst_dec();
reg [3:0] in;
reg oe;
wire [15:0] y;
integer k;
initial begin
 oe = 1;
 #10 oe = 0; in = 0;
 for(k=1; k<=15; k=k+1)
  #10 in = k;
end
decodificator tstd(in, oe, y);
endmodule

module schema();
//parametri numarator
reg [3:0] data;
reg up_down, load, clk, reset, oe;
wire [3:0] result;
wire tc;
//parametri decodificator
wire [15:0] y;
//parametri deplasare
reg rst, s_in, d_in;
reg [1:0] sd;
wire [3:0] q;
initial begin
 clk = 1;
 forever
  #10 clk = ~clk;
end
initial begin
 oe = 1; rst = 0;
 #10 oe = 0; reset = 1;
 #20 reset = 0; load = 1; data = 11; sd = 0;
 #20 load = 0; up_down = 0; d_in = 0; s_in = 1; sd = 2;
 #200 up_down = 1; sd = 1;
 #150 reset = 1;
end
numarator ftstn(data, up_down, load, clk, reset, oe, result, tc);
reg_deplasare ftstr(clk, rst, sd, s_in, d_in, result, q);
decodificator ftstd(result, oe, y);
endmodule