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Oct 9th, 2019
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  1. diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py
  2. index 54c31596..c9fdb0dd 100644
  3. --- a/litex/soc/cores/cpu/rocket/core.py
  4. +++ b/litex/soc/cores/cpu/rocket/core.py
  5. @@ -56,15 +56,17 @@ class RocketRV64(CPU):
  6.      endianness           = "little"
  7.      gcc_triple           = ("riscv64-unknown-elf")
  8.      linker_output_format = "elf64-littleriscv"
  9. -    io_regions           = {0x80000000: 0x80000000} # origin, length
  10. +    io_regions           = {0x10000000: 0x70000000} # origin, length
  11.  
  12.      @property
  13.      def mem_map(self):
  14.          # Rocket reserves the first 256Mbytes for internal use, so we must change default mem_map.
  15.          return {
  16. -            "rom"  : 0x10000000,
  17. -            "sram" : 0x11000000,
  18. -            "csr"  : 0x92000000,
  19. +            "rom"      : 0x10000000,
  20. +            "sram"     : 0x11000000,
  21. +            "csr"      : 0x12000000,
  22. +            "ethmac"   : 0x30000000,
  23. +            "main_ram" : 0x80000000,
  24.          }
  25.  
  26.      @property
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