library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ALU is
	port (  A : in signed(15 downto 0); 							--wejscie
		B : in signed(15 downto 0); 									--wejscie
		Salu : in bit_vector (3 downto 0);
		LDF : in bit; 														--zapis flag
 		clk : in bit;  													--zegar
		Y : out signed (15 downto 0); 								--wyjscie
		C,Z,S,P : out std_logic 										--flagi (C-carry, z-zero, s-sign, p-parity)
	);
end entity;

architecture rtl of ALU is
begin
	process (Salu, A, B, clk)
	    variable res, AA, BB,CC: signed (16 downto 0); 		--argumenty
	    variable CF,ZF,SF,PF : std_logic; 							--flagi
	    variable pp : integer;                          		--bit parzystosci
		 begin
			AA(16) := A(15);
			AA(15 downto 0) := A;
			BB(16) := B(15);
			BB(15 downto 0) := B;
			CC(0) := CF;
			CC(16 downto 1) := "0000000000000000";
		   case Salu is
				when "0000" => res := AA; 										--MOV arg1,arg2
				when "0001" => res := AA + BB; 								--ADD arg1,arg2
				when "0010" => res := AA - BB; 								--SUB arg1,arg2
				when "0011" => if (CC = 0) then								--ST4D arg1,arg2,arg3
							res(3 downto 0) := BB(3 downto 0);
							 else
							res(3 downto 0) := BB(7 downto 4);
							 end if;
				when "0100" => res := AA;										--PUSH arg1
				when "0101" => res := AA;										--POP arg1
				when "0110" => res(15 downto 0) := AA(7 downto 0)*BB(7 downto 0);	--MUL arg1,arg2
				when "0111" => res := -AA;										--NEG arg1
				when "1000" => res := AA;										--JMP etykieta
				when "1111" => res(16) := AA(16);
				when others => null;
				res(15 downto 0) := AA(16 downto 1);
	       end case;

			 Y <= res(15 downto 0);
			 Z <= ZF;
			 S <= SF;
			 C <= CF;
			 if (clk'event and clk='1') then
				if (LDF='1') then
					if (res = "00000000000000000") then ZF:='1';
					else ZF:='0';
					end if;

					if (res(15)='1') then SF:='1';
					else SF:='0';
					end if;
					CF := res(16);

					for i in 1 to 15 loop					--sprawdzenie parzystosci
						if(res(i) = '1') then
							pp := pp+1;
						end if;
					end loop;

					if(pp mod 2 =0) then
						PF := '1';
					else
						PF:= '0';
					end if;

				end if;
			end if;
	end process;
end rtl;