`timescale 1ns/1ps

module divider
  #(
    parameter DIVIDEND_WIDTH = 16,
    parameter DIVISOR_WIDTH = 8,
    parameter QUOTIENT_WIDTH  = 16,
    parameter TWO_STAGE_SUB = 1
  )
  (
    input wire clk,
    input wire start,
    input wire reset,
    input wire [DIVIDEND_WIDTH - 1:0] dividend,
    input wire [DIVISOR_WIDTH - 1:0] divisor,
    output wire [QUOTIENT_WIDTH - 1:0] quotient,
    output reg ready = 1'b1
);

  reg args_comp = 1'b0;
  reg [$clog2(DIVIDEND_WIDTH + 1) - 1:0] cnt = 'b0;

  reg sub_trig = 1'b0;
  reg [DIVIDEND_WIDTH - 1:0] reg_sub = 'b0;
  reg [DIVIDEND_WIDTH - 1:0] dividend_reg = 'b0;
  reg [DIVIDEND_WIDTH + DIVISOR_WIDTH - 2:0] divisor_reg = 'b0;
  reg [DIVIDEND_WIDTH - 1:0] quotient_reg = 'b0;

  assign quotient = quotient_reg[QUOTIENT_WIDTH - 1:0];

  always @(posedge clk) begin
    args_comp <= (divisor_reg <= dividend_reg);
    reg_sub <= dividend_reg - divisor_reg;
  end

  always @(posedge clk) begin
    if (ready) begin
      if (start) begin
        ready <= 1'b0;
        cnt <= 'b0;
        sub_trig <= 1'b0;
        dividend_reg <= dividend;
        quotient_reg <= 'b0;
        divisor_reg <= {divisor, {(DIVIDEND_WIDTH - 1){1'b0}} };
      end
    end else begin
      sub_trig <= !sub_trig;
      if (sub_trig || !TWO_STAGE_SUB) begin
        if (cnt == (DIVIDEND_WIDTH - 1)) begin
          ready <= 1'b1;
        end
        if ((TWO_STAGE_SUB  && args_comp) || (!TWO_STAGE_SUB && (divisor_reg <= dividend_reg))) begin
          dividend_reg <= TWO_STAGE_SUB ? reg_sub : (dividend_reg - divisor_reg);
          quotient_reg <= (quotient_reg << 1) | 1'b1;
        end else begin
          quotient_reg <= (quotient_reg << 1);
        end
        divisor_reg <= divisor_reg >> 1;
        cnt <= cnt + 1'b1;
      end
    end
  end
endmodule