Modified Booth + TB

module booth_modificat
#( parameter OPERAND_BITS = 8,
parameter RESULT_BITS = 16)
(

input clk,
input rst,
input [OPERAND_BITS - 1 : 0] a,
input [OPERAND_BITS - 1 : 0] b,
input start,
output[RESULT_BITS - 1 : 0] result,
output reg ovr,
output [3:0] st,
output [3:0] st_nxt
);

reg f;
reg [OPERAND_BITS-1 : 0] A;
reg [OPERAND_BITS : 0] Q;
reg Q_1;
reg [OPERAND_BITS-1 : 0] M;
reg [2:0] count;

reg [3:0] state;
reg [3:0] state_nxt;

localparam [3:0] s0=3'd0, s1=3'd1, s2=3'd2, s3=3'd3, s4=3'd4, s5=3'd5, s6=3'd6, s7=3'd7, s8=3'd8, s9=3'd9;

// sequential process

always @(posedge clk)
   state <= state_nxt;

always
@(posedge clk, posedge rst)

begin

if (rst)

begin

// do something

end

else

begin
   case(state)
       s0: ;
       s1:
          begin
              A = 0;
              count = 0;
              f = 0;
              ovr = 0;
              M = a;
          end
       s2:
          begin
              Q = b[7:0];
              Q_1 = b[0];
          end
       s3:
          begin
              Q = 0;
              Q_1 = 0;
          end
       s4:
          begin
              if(f == 0)
               begin
                 if(Q[7] == 1)
                    if(Q[6] == 0)
                    begin
                        A = A + M;
                        ovr = 1'b1;
                    end
                    else
                    begin
                        A = A - M;
                        ovr = 1'b1;
                        f = 1'b1;
                    end
               end
               else
               begin
                   if(Q[7] == 1)
                      if(Q[6] == 0)
                      begin
                          A = A + M;
                          ovr = 1'b1;
                          f = 1'b0;
                      end
                      else
                      begin
                          A = A - M;
                          ovr = 1'b1;
                      end
               end
          end
       s8:
          begin
              A[7] = f ^ M[7];
              {A[7:1], Q} = {A, Q[6:0], Q_1};
              count = count + 1'b1;
          end
       s9:
          begin
             Q[6] = 0;
          end
   endcase
// do something

end
end



// combinational process

always

@(start, state, count)

begin
   state_nxt = 2'b0;
// create state machine
   case(state)
    s0:
      if(start)
        state_nxt = s1;
      else
        state_nxt = s0;
    s1:
      state_nxt = s2;
    s2:
      //if(Q == 0)
        state_nxt = s9;
      //else
      //   if(M == 0)
       //    state_nxt = s3;
       //  else
       //     state_nxt = s4;
    s3:
      state_nxt = s9;
    s4:
      if(count == 2'd7)
        state_nxt = s9;
      else
        state_nxt = s8;
    s8:
      state_nxt = s4;
    s9:
       ;

  endcase
  $display("DB: %b %b", A, Q, M, state, state_nxt) ;
// determine values for all signals in each state

end

assign result = {A, Q[6:0], Q_1};
assign st = state;
assign st_nxt = state_nxt;

endmodule


//TB

module booth_modificat_tb

#( parameter OPERAND_BITS = 8,
parameter RESULT_BITS = 16)

(
output reg clk,
output reg rst,
output reg start,

output reg [OPERAND_BITS - 1 : 0] a,
output reg [OPERAND_BITS - 1 : 0] b,

output [RESULT_BITS - 1 : 0] result,
output ovr,
output [3:0] st,
output [3:0] st_nxt
);

booth_modificat b1(
   .clk(clk),
   .rst(rst),
   .start(start),
   .a(a),
   .b(b),
   .result(result),
   .ovr(ovr),
   .st(st),
   .st_nxt(st_nxt)
);

initial begin
      clk = 0;
      repeat (30) #50 clk = ~clk;
end

initial begin
   a = 8'd2;
   b = 8'd3;
end

initial begin
   start = 1'b0;
   #50 start = 1'b1;
end

initial begin
    rst = 1'b0;
end

initial begin
   $monitor("@%1t: clk=%b, start=%b, result=%b, rst=%b a=%b, b=%b, st=%b, st_nxt=%b", $time, clk, start, result, rst, a, b, st, st_nxt);
end

endmodule