`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:    11:40:13 04/05/2017
// Design Name:
// Module Name:    ctrlpush
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ctrlpush(
    input clk,
    input reset,
    input start,
    input [7:0] mdout,
    input [7:0] size,
	 input [7:0] din,
    output sizeinc,
    output mwen,
    output [7:0] maddr,
    output [7:0] mdin,
    output done
    );

/* STATE MACHINE */
// registers for one-hot
wire d_idle, d_init, d_parent, d_comp, d_done;
wire q_idle, q_init, q_parent, q_comp, q_done;

dff1s dff_idle(.clk(clk),
				 .clr(1'b0),
				 .set(reset),
				 .d(d_idle),
				 .q(q_idle) );
dff1s dff_init(.clk(clk),
					.clr(reset),
					.set(1'b0),
					.d(d_init),
					.q(q_init) );
dff1s dff_parent(.clk(clk),
					  .clr(reset),
					  .set(1'b0),
					  .d(d_parent),
					  .q(q_parent) );
dff1s dff_comp(.clk(clk),
					.clr(reset),
					.set(1'b0),
					.d(d_comp),
					.q(q_comp) );
dff1s dff_done(.clk(clk),
					.clr(reset),
					.set(1'b0),
					.d(d_done),
					.q(q_done) );

// state logic
assign d_idle = (q_done) | (q_idle & ~start);
assign d_init = (q_idle & start);
assign d_parent = (q_init & size_gt_0) | (q_comp & din_lt_p & ~idx_div2_eq_1);
assign d_comp = (q_parent);
assign d_done = (q_comp & (din_gte_p | idx_div2_eq_1)) | (q_init & ~size_gt_0);

// state logic components
wire size_gt_0, din_lt_p, idx_div2_eq_1, din_gte_p;
assign size_gt_0 = (size[7:0] > 0);
assign din_lt_p = (din[7:0] < p[7:0]);
assign idx_div2_eq_1 = ({1'b0, idx[7:1]} == 1);
assign din_gte_p = (din[7:0] >= p[7:0]);

/* DATAPATH */
// registers
reg [7:0]d_idx; // memory address
wire [7:0]idx;
reg8e reg_idx(.clk(clk),
				  .reset(reset),
				  .en(q_init | q_comp),
				  .d(d_idx),
				  .q(idx) );

wire [7:0]p; // value of parent
reg8e reg_p(.clk(clk),
				  .reset(reset),
				  .en(q_init | q_parent),
				  .d(mdout),
				  .q(p) );

reg [7:0]d_maddr;
reg [7:0]d_mdin;
reg d_mwen;

always @ (q_idle or q_init or q_parent or q_comp or q_done or din_lt_p)
if(q_idle) begin
	// do nothing
	d_idx = 8'b00000000;
	d_maddr = 8'b00000000;
	d_mdin = 8'b00000000;
	d_mwen = 1'b0;
end else if(q_init) begin
	d_mwen = 1'b0;
	d_idx = size[7:0] + 1;
end else if(q_parent) begin
	d_maddr = {1'b0, d_idx[7:1]};
	d_mwen = 1'b0;
end else if(q_comp) begin
	if(din_lt_p) begin
		d_mwen = 1'b1;
		d_maddr = idx[7:0];
		d_mdin = p[7:0];
		d_idx = {1'b0, idx[7:1]};
	end
end else if(q_done) begin
	d_mwen = 1'b1;
	d_maddr = idx[7:0];
	d_mdin = din[7:0];
end

assign sizeinc = q_init;
assign done = q_done;
assign maddr = d_maddr;
assign mdin = d_mdin;
assign mwen = d_mwen;

endmodule