module zad3(
    input CLOCK_50,
    input [7:0] SW,
    input [0:3] KEY,
    output [0:6] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5);

    wire unitsSetToDozensSet, dozensSetToUnitsSek, unitsSekToDozensSek;
    wire dozensSekToUnitsMin, unitsMinToDozensMin;
    wire clk, terminator;
    wire [3:0] unitsSetHex, dozensSetHex, unitsSekHex, dozensSekHex, unitsMinHex, dozensMinHex;

    counter_to_make_delay_10_ms(CLOCK_50, 1, clk);

    counter_mod_M_rollover_aload #(10) setUnits(clk,1, KEY[0],KEY[1],SW[3:0],unitsSetHex,unitsSetToDozensSet);
    counter_mod_M_rollover_aload #(10) setDozens(unitsSetToDozensSet,1, 1,KEY[1],SW[7:4],dozensSetHex,dozensSetToUnitsSek);

    counter_mod_M_rollover_aload #(10) sekUnits(dozensSetToUnitsSek,1,1,KEY[2],SW[3:0],unitsSekHex,unitsSekToDozensSek);
    counter_mod_M_rollover_aload #(6) sekDozens(unitsSekToDozensSek,1, 1,KEY[2],SW[7:4],dozensSekHex,dozensSekToUnitsMin);

    counter_mod_M_rollover_aload #(10) minUnits(dozensSekToUnitsMin,1,1,KEY[3],SW[3:0],unitsMinHex,unitsMinToDozensMin);
    counter_mod_M_rollover_aload #(6) minDozens(unitsMinToDozensMin,1, 1,KEY[3],SW[7:4],dozensMinHex,terminator);

    decoder_hex_10 ex1(unitsSetHex,HEX0);
    decoder_hex_10 ex2(dozensSetHex,HEX1);
    decoder_hex_10 ex3(unitsSekHex,HEX2);
    decoder_hex_10 ex4(dozensSekHex,HEX3);
    decoder_hex_10 ex5(unitsMinHex,HEX4);
    decoder_hex_10 ex6(dozensMinHex,HEX5);

endmodule

module counter_to_make_delay_10_ms(
    input clk, aclr,
    output reg clockTact);

    reg [25:0] i;

    always@(posedge clk, negedge aclr)
        if(!aclr)
            begin
                i<=0;
                clockTact<=0;
            end
        else
            begin
                if(i==2)
                    begin
                        i<=0;
                        clockTact<=1;
                    end
                else
                    begin
                        i<=i+1;
                        clockTact<=0;
                    end
            end

endmodule

module counter_mod_M_rollover_aload
    #(parameter M=16)
    (input clk, aclr, enable, aload,
    input [N-1:0] data,
    output reg [N-1:0] Q={N{1'b0}},
    output reg rollover=0);

    localparam N=clogb2(M-1);
    function integer clogb2(input [31:0] v);
        for(clogb2=0;v>0;clogb2=clogb2+1)
            v=v>>1;
    endfunction

    always@(posedge clk, negedge aclr, posedge aload)
        if(!aclr) Q<={N{1'b0}};
        else if(aload) Q<=data;
        else if(Q==M-1)
            begin
                Q<={N{1'b0}};
                rollover<=1;
            end
        else if(enable)
            begin
                Q<=Q+1'b1;
                rollover<=0;
            end
        else Q<=Q;

endmodule