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- OrangePi one plus (H6)
- tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
- ==========================================================================
- == Memory bandwidth tests ==
- == ==
- == Note 1: 1MB = 1000000 bytes ==
- == Note 2: Results for 'copy' tests show how many bytes can be ==
- == copied per second (adding together read and writen ==
- == bytes would have provided twice higher numbers) ==
- == Note 3: 2-pass copy means that we are using a small temporary buffer ==
- == to first fetch data into it, and only then write it to the ==
- == destination (source -> L1 cache, L1 cache -> destination) ==
- == Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
- == brackets ==
- ==========================================================================
- C copy backwards : 1597.0 MB/s (16.0%)
- C copy backwards (32 byte blocks) : 1635.7 MB/s (1.3%)
- C copy backwards (64 byte blocks) : 1628.8 MB/s (1.1%)
- C copy : 1616.4 MB/s (0.6%)
- C copy prefetched (32 bytes step) : 1220.3 MB/s
- C copy prefetched (64 bytes step) : 1215.9 MB/s
- C 2-pass copy : 1471.7 MB/s
- C 2-pass copy prefetched (32 bytes step) : 1060.6 MB/s
- C 2-pass copy prefetched (64 bytes step) : 954.4 MB/s
- C fill : 5679.0 MB/s
- C fill (shuffle within 16 byte blocks) : 5681.3 MB/s
- C fill (shuffle within 32 byte blocks) : 5683.7 MB/s
- C fill (shuffle within 64 byte blocks) : 5683.3 MB/s
- ---
- standard memcpy : 1652.0 MB/s
- standard memset : 5685.0 MB/s
- ---
- NEON LDP/STP copy : 1646.3 MB/s (0.3%)
- NEON LDP/STP copy pldl2strm (32 bytes step) : 1114.1 MB/s (1.1%)
- NEON LDP/STP copy pldl2strm (64 bytes step) : 1366.6 MB/s (0.2%)
- NEON LDP/STP copy pldl1keep (32 bytes step) : 1756.2 MB/s
- NEON LDP/STP copy pldl1keep (64 bytes step) : 1746.1 MB/s
- NEON LD1/ST1 copy : 1640.8 MB/s
- NEON STP fill : 5685.8 MB/s
- NEON STNP fill : 2988.4 MB/s (1.1%)
- ARM LDP/STP copy : 1645.1 MB/s (0.3%)
- ARM STP fill : 5683.5 MB/s
- ARM STNP fill : 2988.5 MB/s (0.8%)
- ==========================================================================
- == Framebuffer read tests. ==
- == ==
- == Many ARM devices use a part of the system memory as the framebuffer, ==
- == typically mapped as uncached but with write-combining enabled. ==
- == Writes to such framebuffers are quite fast, but reads are much ==
- == slower and very sensitive to the alignment and the selection of ==
- == CPU instructions which are used for accessing memory. ==
- == ==
- == Many x86 systems allocate the framebuffer in the GPU memory, ==
- == accessible for the CPU via a relatively slow PCI-E bus. Moreover, ==
- == PCI-E is asymmetric and handles reads a lot worse than writes. ==
- == ==
- == If uncached framebuffer reads are reasonably fast (at least 100 MB/s ==
- == or preferably >300 MB/s), then using the shadow framebuffer layer ==
- == is not necessary in Xorg DDX drivers, resulting in a nice overall ==
- == performance improvement. For example, the xf86-video-fbturbo DDX ==
- == uses this trick. ==
- ==========================================================================
- NEON LDP/STP copy (from framebuffer) : 217.9 MB/s
- NEON LDP/STP 2-pass copy (from framebuffer) : 209.7 MB/s
- NEON LD1/ST1 copy (from framebuffer) : 56.6 MB/s
- NEON LD1/ST1 2-pass copy (from framebuffer) : 56.1 MB/s
- ARM LDP/STP copy (from framebuffer) : 110.6 MB/s
- ARM LDP/STP 2-pass copy (from framebuffer) : 108.2 MB/s
- ==========================================================================
- == Memory latency test ==
- == ==
- == Average time is measured for random memory accesses in the buffers ==
- == of different sizes. The larger is the buffer, the more significant ==
- == are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
- == accesses. For extremely large buffer sizes we are expecting to see ==
- == page table walk with several requests to SDRAM for almost every ==
- == memory access (though 64MiB is not nearly large enough to experience ==
- == this effect to its fullest). ==
- == ==
- == Note 1: All the numbers are representing extra time, which needs to ==
- == be added to L1 cache latency. The cycle timings for L1 cache ==
- == latency can be usually found in the processor documentation. ==
- == Note 2: Dual random read means that we are simultaneously performing ==
- == two independent memory accesses at a time. In the case if ==
- == the memory subsystem can't handle multiple outstanding ==
- == requests, dual random read has the same timings as two ==
- == single reads performed one after another. ==
- ==========================================================================
- block size : single random read / dual random read
- 1024 : 0.0 ns / 0.0 ns
- 2048 : 0.0 ns / 0.0 ns
- 4096 : 0.0 ns / 0.0 ns
- 8192 : 0.0 ns / 0.0 ns
- 16384 : 0.0 ns / 0.0 ns
- 32768 : 0.0 ns / 0.0 ns
- 65536 : 3.8 ns / 6.4 ns
- 131072 : 5.8 ns / 8.9 ns
- 262144 : 6.9 ns / 10.2 ns
- 524288 : 8.0 ns / 11.1 ns
- 1048576 : 74.7 ns / 115.1 ns
- 2097152 : 110.0 ns / 148.5 ns
- 4194304 : 132.3 ns / 164.9 ns
- 8388608 : 144.7 ns / 174.3 ns
- 16777216 : 152.0 ns / 179.4 ns
- 33554432 : 156.3 ns / 182.9 ns
- 67108864 : 158.5 ns / 184.9 ns
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