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- NOTICE: BL31: Built : 00:39:03, Jul 21 2019
- INFO: Changed device tree to advertise PSCI.
- INFO: ARM GICv2 driver initialized
- INFO: BL31: Initializing runtime services
- INFO: BL31: cortex_a72: CPU workaround for 859971 was applied
- INFO: BL31: cortex_a72: CPU workaround for cve_2017_5715 was applied
- INFO: BL31: cortex_a72: CPU workaround for cve_2018_3639 was applied
- INFO: BL31: Preparing for EL3 exit to normal world
- INFO: Entry point address = 0x80000
- INFO: SPSR = 0x3c9
- Xen 4.13-unstable
- (XEN) Xen version 4.13-unstable (aprzywara@lan) (aarch64-slackware-linux-gcc (GCC) 7.3.0) debug=y Sun Jul 21 00:42:38 BST 2019
- (XEN) Latest ChangeSet: Fri May 17 11:08:56 2019 +0100 git:38eeb3864d-dirty
- (XEN) build-id: a42c3eb1e96682b9686703a59771f695ba4de7d4
- (XEN) Processor: 410fd083: "ARM Limited", variant: 0x0, part 0xd08, rev 0x3
- (XEN) 64-bit Execution:
- (XEN) Processor Features: 0000000000002222 0000000000000000
- (XEN) Exception Levels: EL3:64+32 EL2:64+32 EL1:64+32 EL0:64+32
- (XEN) Extensions: FloatingPoint AdvancedSIMD
- (XEN) Debug Features: 0000000010305106 0000000000000000
- (XEN) Auxiliary Features: 0000000000000000 0000000000000000
- (XEN) Memory Model Features: 0000000000001124 0000000000000000
- (XEN) ISA Features: 0000000000010000 0000000000000000
- (XEN) 32-bit Execution:
- (XEN) Processor Features: 00000131:00011011
- (XEN) Instruction Sets: AArch32 A32 Thumb Thumb-2 Jazelle
- (XEN) Extensions: GenericTimer Security
- (XEN) Debug Features: 03010066
- (XEN) Auxiliary Features: 00000000
- (XEN) Memory Model Features: 10201105 40000000 01260000 02102211
- (XEN) ISA Features: 02101110 13112111 21232042 01112131 00011142 00010001
- (XEN) Using SMC Calling Convention v1.1
- (XEN) Using PSCI v1.1
- (XEN) SMP: Allowing 4 CPUs
- (XEN) Generic Timer IRQ: phys=30 hyp=26 virt=27 Freq: 2700 KHz
- (XEN) GICv2 initialization:
- (XEN) gic_dist_addr=00000000ff841000
- (XEN) gic_cpu_addr=00000000ff842000
- (XEN) gic_hyp_addr=00000000ff844000
- (XEN) gic_vcpu_addr=00000000ff846000
- (XEN) gic_maintenance_irq=25
- (XEN) GICv2: 256 lines, 4 cpus, secure (IID 0200143b).
- (XEN) Using scheduler: SMP Credit Scheduler rev2 (credit2)
- (XEN) Initializing Credit2 scheduler
- (XEN) load_precision_shift: 18
- (XEN) load_window_shift: 30
- (XEN) underload_balance_tolerance: 0
- (XEN) overload_balance_tolerance: -3
- (XEN) runqueues arrangement: socket
- (XEN) cap enforcement granularity: 10ms
- (XEN) load tracking window length 1073741824 ns
- (XEN) Adding cpu 0 to runqueue 0
- (XEN) First cpu on runqueue, activating
- (XEN) Allocated console ring of 32 KiB.
- (XEN) CPU0: Guest atomics will try 5 times before pausing the domain
- (XEN) Bringing up CPU1
- (XEN) Adding cpu 1 to runqueue 0
- (XEN) CPU1: Guest atomics will try 4 times before pausing the domain
- (XEN) CPU 1 booted.
- (XEN) Bringing up CPU2
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