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CPU Info

teknogeek
Jan 1st, 2014
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  1. CPU 0:
  2. vendor_id = "GenuineIntel"
  3. version information (1/eax):
  4. processor type = primary processor (0)
  5. family = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
  6. model = 0xd (13)
  7. stepping id = 0x3 (3)
  8. extended family = 0x0 (0)
  9. extended model = 0x0 (0)
  10. (simple synth) = Intel Pentium M (Dothan) / Celeron M (Dothan) / Pentium M (Crofton), 90nm
  11. miscellaneous (1/ebx):
  12. process local APIC physical ID = 0x0 (0)
  13. cpu count = 0x0 (0)
  14. CLFLUSH line size = 0x8 (8)
  15. brand index = 0x0 (0)
  16. brand id = 0x00 (0): unknown
  17. feature information (1/edx):
  18. x87 FPU on chip = true
  19. virtual-8086 mode enhancement = false
  20. debugging extensions = true
  21. page size extensions = true
  22. time stamp counter = true
  23. RDMSR and WRMSR support = true
  24. physical address extensions = true
  25. machine check exception = true
  26. CMPXCHG8B inst. = true
  27. APIC on chip = true
  28. SYSENTER and SYSEXIT = false
  29. memory type range registers = true
  30. PTE global bit = true
  31. machine check architecture = true
  32. conditional move/compare instruction = true
  33. page attribute table = true
  34. page size extension = true
  35. processor serial number = false
  36. CLFLUSH instruction = true
  37. debug store = false
  38. thermal monitor and clock ctrl = false
  39. MMX Technology = true
  40. FXSAVE/FXRSTOR = true
  41. SSE extensions = true
  42. SSE2 extensions = true
  43. self snoop = false
  44. hyper-threading / multi-core supported = false
  45. therm. monitor = false
  46. IA64 = false
  47. pending break event = false
  48. feature information (1/ecx):
  49. PNI/SSE3: Prescott New Instructions = true
  50. PCLMULDQ instruction = false
  51. 64-bit debug store = false
  52. MONITOR/MWAIT = false
  53. CPL-qualified debug store = false
  54. VMX: virtual machine extensions = false
  55. SMX: safer mode extensions = false
  56. Enhanced Intel SpeedStep Technology = false
  57. thermal monitor 2 = false
  58. SSSE3 extensions = false
  59. context ID: adaptive or shared L1 data = false
  60. FMA instruction = false
  61. CMPXCHG16B instruction = true
  62. xTPR disable = false
  63. perfmon and debug = false
  64. process context identifiers = false
  65. direct cache access = false
  66. SSE4.1 extensions = false
  67. SSE4.2 extensions = false
  68. extended xAPIC support = false
  69. MOVBE instruction = false
  70. POPCNT instruction = false
  71. time stamp counter deadline = false
  72. AES instruction = false
  73. XSAVE/XSTOR states = false
  74. OS-enabled XSAVE/XSTOR = false
  75. AVX: advanced vector extensions = false
  76. F16C half-precision convert instruction = false
  77. RDRAND instruction = false
  78. hypervisor guest status = true
  79. cache and TLB information (2):
  80. 0x7d: L2 cache: 2M, 8-way, sectored, 64 byte lines
  81. 0x30: L1 cache: 32K, 8-way, 64 byte lines
  82. 0x2c: L1 data cache: 32K, 8-way, 64 byte lines
  83. processor serial number: 0000-06D3-0000-0000-0000-0000
  84. deterministic cache parameters (4):
  85. --- cache 0 ---
  86. cache type = data cache (1)
  87. cache level = 0x1 (1)
  88. self-initializing cache level = true
  89. fully associative cache = false
  90. extra threads sharing this cache = 0x0 (0)
  91. extra processor cores on this die = 0x0 (0)
  92. system coherency line size = 0x3f (63)
  93. physical line partitions = 0x0 (0)
  94. ways of associativity = 0x7 (7)
  95. WBINVD/INVD behavior on lower caches = true
  96. inclusive to lower caches = false
  97. complex cache indexing = false
  98. number of sets - 1 (s) = 63
  99. --- cache 1 ---
  100. cache type = instruction cache (2)
  101. cache level = 0x1 (1)
  102. self-initializing cache level = true
  103. fully associative cache = false
  104. extra threads sharing this cache = 0x0 (0)
  105. extra processor cores on this die = 0x0 (0)
  106. system coherency line size = 0x3f (63)
  107. physical line partitions = 0x0 (0)
  108. ways of associativity = 0x7 (7)
  109. WBINVD/INVD behavior on lower caches = true
  110. inclusive to lower caches = false
  111. complex cache indexing = false
  112. number of sets - 1 (s) = 63
  113. --- cache 2 ---
  114. cache type = unified cache (3)
  115. cache level = 0x2 (2)
  116. self-initializing cache level = true
  117. fully associative cache = false
  118. extra threads sharing this cache = 0x0 (0)
  119. extra processor cores on this die = 0x0 (0)
  120. system coherency line size = 0x3f (63)
  121. physical line partitions = 0x0 (0)
  122. ways of associativity = 0xf (15)
  123. WBINVD/INVD behavior on lower caches = true
  124. inclusive to lower caches = false
  125. complex cache indexing = false
  126. number of sets - 1 (s) = 4095
  127. hypervisor_id = "KVMKVMKVM "
  128. hypervisor features (0x40000001/eax):
  129. kvmclock available at MSR 0x11 = true
  130. delays unnecessary for PIO ops = true
  131. mmu_op = false
  132. kvmclock available a MSR 0x4b564d00 = true
  133. async pf enable available by MSR = false
  134. steal clock supported = true
  135. guest EOI optimization enabled = true
  136. stable: no guest per-cpu warps expected = true
  137. extended feature flags (0x80000001/edx):
  138. SYSCALL and SYSRET instructions = true
  139. execution disable = true
  140. 1-GB large page support = false
  141. RDTSCP = false
  142. 64-bit extensions technology available = true
  143. Intel feature flags (0x80000001/ecx):
  144. LAHF/SAHF supported in 64-bit mode = true
  145. brand = "QEMU Virtual CPU version (cpu64-rhel6)"
  146. L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
  147. instruction # entries = 0xff (255)
  148. instruction associativity = 0x1 (1)
  149. data # entries = 0xff (255)
  150. data associativity = 0x1 (1)
  151. L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
  152. instruction # entries = 0xff (255)
  153. instruction associativity = 0x1 (1)
  154. data # entries = 0xff (255)
  155. data associativity = 0x1 (1)
  156. L1 data cache information (0x80000005/ecx):
  157. line size (bytes) = 0x40 (64)
  158. lines per tag = 0x1 (1)
  159. associativity = 0x2 (2)
  160. size (Kb) = 0x40 (64)
  161. L1 instruction cache information (0x80000005/edx):
  162. line size (bytes) = 0x40 (64)
  163. lines per tag = 0x1 (1)
  164. associativity = 0x2 (2)
  165. size (Kb) = 0x40 (64)
  166. L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
  167. instruction # entries = 0x0 (0)
  168. instruction associativity = L2 off (0)
  169. data # entries = 0x0 (0)
  170. data associativity = L2 off (0)
  171. L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
  172. instruction # entries = 0x200 (512)
  173. instruction associativity = 4-way (4)
  174. data # entries = 0x200 (512)
  175. data associativity = 4-way (4)
  176. L2 unified cache information (0x80000006/ecx):
  177. line size (bytes) = 0x40 (64)
  178. lines per tag = 0x1 (1)
  179. associativity = 16-way (8)
  180. size (Kb) = 0x200 (512)
  181. L3 cache information (0x80000006/edx):
  182. line size (bytes) = 0x0 (0)
  183. lines per tag = 0x0 (0)
  184. associativity = L2 off (0)
  185. size (in 512Kb units) = 0x0 (0)
  186. Advanced Power Management Features (0x80000007/edx):
  187. temperature sensing diode = false
  188. frequency ID (FID) control = false
  189. voltage ID (VID) control = false
  190. thermal trip (TTP) = false
  191. thermal monitor (TM) = false
  192. software thermal control (STC) = false
  193. 100 MHz multiplier control = false
  194. hardware P-State control = false
  195. TscInvariant = false
  196. Physical Address and Linear Address Size (0x80000008/eax):
  197. maximum physical address bits = 0x28 (40)
  198. maximum linear (virtual) address bits = 0x30 (48)
  199. maximum guest physical address bits = 0x0 (0)
  200. Logical CPU cores (0x80000008/ecx):
  201. number of CPU cores - 1 = 0x0 (0)
  202. ApicIdCoreIdSize = 0x0 (0)
  203. SVM Secure Virtual Machine (0x8000000a/eax):
  204. SvmRev: SVM revision = 0x1 (1)
  205. SVM Secure Virtual Machine (0x8000000a/edx):
  206. nested paging = false
  207. LBR virtualization = false
  208. SVM lock = false
  209. NRIP save = false
  210. MSR based TSC rate control = false
  211. VMCB clean bits support = false
  212. flush by ASID = false
  213. decode assists = false
  214. SSSE3/SSE5 opcode set disable = false
  215. pause intercept filter = false
  216. pause filter threshold = false
  217. NASID: number of address space identifiers = 0x10 (16):
  218. (multi-processing synth): none
  219. (multi-processing method): Intel leaf 1/4
  220. (APIC widths synth): CORE_width=0 SMT_width=16
  221. (APIC synth): PKG_ID=8 CORE_ID=8 SMT_ID=0
  222. (synth) = Intel Pentium M (Dothan) / Celeron M (Dothan) / Pentium M (Crofton), 90nm
  223. CPU 1:
  224. vendor_id = "GenuineIntel"
  225. version information (1/eax):
  226. processor type = primary processor (0)
  227. family = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
  228. model = 0xd (13)
  229. stepping id = 0x3 (3)
  230. extended family = 0x0 (0)
  231. extended model = 0x0 (0)
  232. (simple synth) = Intel Pentium M (Dothan) / Celeron M (Dothan) / Pentium M (Crofton), 90nm
  233. miscellaneous (1/ebx):
  234. process local APIC physical ID = 0x1 (1)
  235. cpu count = 0x0 (0)
  236. CLFLUSH line size = 0x8 (8)
  237. brand index = 0x0 (0)
  238. brand id = 0x00 (0): unknown
  239. feature information (1/edx):
  240. x87 FPU on chip = true
  241. virtual-8086 mode enhancement = false
  242. debugging extensions = true
  243. page size extensions = true
  244. time stamp counter = true
  245. RDMSR and WRMSR support = true
  246. physical address extensions = true
  247. machine check exception = true
  248. CMPXCHG8B inst. = true
  249. APIC on chip = true
  250. SYSENTER and SYSEXIT = false
  251. memory type range registers = true
  252. PTE global bit = true
  253. machine check architecture = true
  254. conditional move/compare instruction = true
  255. page attribute table = true
  256. page size extension = true
  257. processor serial number = false
  258. CLFLUSH instruction = true
  259. debug store = false
  260. thermal monitor and clock ctrl = false
  261. MMX Technology = true
  262. FXSAVE/FXRSTOR = true
  263. SSE extensions = true
  264. SSE2 extensions = true
  265. self snoop = false
  266. hyper-threading / multi-core supported = false
  267. therm. monitor = false
  268. IA64 = false
  269. pending break event = false
  270. feature information (1/ecx):
  271. PNI/SSE3: Prescott New Instructions = true
  272. PCLMULDQ instruction = false
  273. 64-bit debug store = false
  274. MONITOR/MWAIT = false
  275. CPL-qualified debug store = false
  276. VMX: virtual machine extensions = false
  277. SMX: safer mode extensions = false
  278. Enhanced Intel SpeedStep Technology = false
  279. thermal monitor 2 = false
  280. SSSE3 extensions = false
  281. context ID: adaptive or shared L1 data = false
  282. FMA instruction = false
  283. CMPXCHG16B instruction = true
  284. xTPR disable = false
  285. perfmon and debug = false
  286. process context identifiers = false
  287. direct cache access = false
  288. SSE4.1 extensions = false
  289. SSE4.2 extensions = false
  290. extended xAPIC support = false
  291. MOVBE instruction = false
  292. POPCNT instruction = false
  293. time stamp counter deadline = false
  294. AES instruction = false
  295. XSAVE/XSTOR states = false
  296. OS-enabled XSAVE/XSTOR = false
  297. AVX: advanced vector extensions = false
  298. F16C half-precision convert instruction = false
  299. RDRAND instruction = false
  300. hypervisor guest status = true
  301. cache and TLB information (2):
  302. 0x7d: L2 cache: 2M, 8-way, sectored, 64 byte lines
  303. 0x30: L1 cache: 32K, 8-way, 64 byte lines
  304. 0x2c: L1 data cache: 32K, 8-way, 64 byte lines
  305. processor serial number: 0000-06D3-0000-0000-0000-0000
  306. deterministic cache parameters (4):
  307. --- cache 0 ---
  308. cache type = data cache (1)
  309. cache level = 0x1 (1)
  310. self-initializing cache level = true
  311. fully associative cache = false
  312. extra threads sharing this cache = 0x0 (0)
  313. extra processor cores on this die = 0x0 (0)
  314. system coherency line size = 0x3f (63)
  315. physical line partitions = 0x0 (0)
  316. ways of associativity = 0x7 (7)
  317. WBINVD/INVD behavior on lower caches = true
  318. inclusive to lower caches = false
  319. complex cache indexing = false
  320. number of sets - 1 (s) = 63
  321. --- cache 1 ---
  322. cache type = instruction cache (2)
  323. cache level = 0x1 (1)
  324. self-initializing cache level = true
  325. fully associative cache = false
  326. extra threads sharing this cache = 0x0 (0)
  327. extra processor cores on this die = 0x0 (0)
  328. system coherency line size = 0x3f (63)
  329. physical line partitions = 0x0 (0)
  330. ways of associativity = 0x7 (7)
  331. WBINVD/INVD behavior on lower caches = true
  332. inclusive to lower caches = false
  333. complex cache indexing = false
  334. number of sets - 1 (s) = 63
  335. --- cache 2 ---
  336. cache type = unified cache (3)
  337. cache level = 0x2 (2)
  338. self-initializing cache level = true
  339. fully associative cache = false
  340. extra threads sharing this cache = 0x0 (0)
  341. extra processor cores on this die = 0x0 (0)
  342. system coherency line size = 0x3f (63)
  343. physical line partitions = 0x0 (0)
  344. ways of associativity = 0xf (15)
  345. WBINVD/INVD behavior on lower caches = true
  346. inclusive to lower caches = false
  347. complex cache indexing = false
  348. number of sets - 1 (s) = 4095
  349. hypervisor_id = "KVMKVMKVM "
  350. hypervisor features (0x40000001/eax):
  351. kvmclock available at MSR 0x11 = true
  352. delays unnecessary for PIO ops = true
  353. mmu_op = false
  354. kvmclock available a MSR 0x4b564d00 = true
  355. async pf enable available by MSR = false
  356. steal clock supported = true
  357. guest EOI optimization enabled = true
  358. stable: no guest per-cpu warps expected = true
  359. extended feature flags (0x80000001/edx):
  360. SYSCALL and SYSRET instructions = true
  361. execution disable = true
  362. 1-GB large page support = false
  363. RDTSCP = false
  364. 64-bit extensions technology available = true
  365. Intel feature flags (0x80000001/ecx):
  366. LAHF/SAHF supported in 64-bit mode = true
  367. brand = "QEMU Virtual CPU version (cpu64-rhel6)"
  368. L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
  369. instruction # entries = 0xff (255)
  370. instruction associativity = 0x1 (1)
  371. data # entries = 0xff (255)
  372. data associativity = 0x1 (1)
  373. L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
  374. instruction # entries = 0xff (255)
  375. instruction associativity = 0x1 (1)
  376. data # entries = 0xff (255)
  377. data associativity = 0x1 (1)
  378. L1 data cache information (0x80000005/ecx):
  379. line size (bytes) = 0x40 (64)
  380. lines per tag = 0x1 (1)
  381. associativity = 0x2 (2)
  382. size (Kb) = 0x40 (64)
  383. L1 instruction cache information (0x80000005/edx):
  384. line size (bytes) = 0x40 (64)
  385. lines per tag = 0x1 (1)
  386. associativity = 0x2 (2)
  387. size (Kb) = 0x40 (64)
  388. L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
  389. instruction # entries = 0x0 (0)
  390. instruction associativity = L2 off (0)
  391. data # entries = 0x0 (0)
  392. data associativity = L2 off (0)
  393. L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
  394. instruction # entries = 0x200 (512)
  395. instruction associativity = 4-way (4)
  396. data # entries = 0x200 (512)
  397. data associativity = 4-way (4)
  398. L2 unified cache information (0x80000006/ecx):
  399. line size (bytes) = 0x40 (64)
  400. lines per tag = 0x1 (1)
  401. associativity = 16-way (8)
  402. size (Kb) = 0x200 (512)
  403. L3 cache information (0x80000006/edx):
  404. line size (bytes) = 0x0 (0)
  405. lines per tag = 0x0 (0)
  406. associativity = L2 off (0)
  407. size (in 512Kb units) = 0x0 (0)
  408. Advanced Power Management Features (0x80000007/edx):
  409. temperature sensing diode = false
  410. frequency ID (FID) control = false
  411. voltage ID (VID) control = false
  412. thermal trip (TTP) = false
  413. thermal monitor (TM) = false
  414. software thermal control (STC) = false
  415. 100 MHz multiplier control = false
  416. hardware P-State control = false
  417. TscInvariant = false
  418. Physical Address and Linear Address Size (0x80000008/eax):
  419. maximum physical address bits = 0x28 (40)
  420. maximum linear (virtual) address bits = 0x30 (48)
  421. maximum guest physical address bits = 0x0 (0)
  422. Logical CPU cores (0x80000008/ecx):
  423. number of CPU cores - 1 = 0x0 (0)
  424. ApicIdCoreIdSize = 0x0 (0)
  425. SVM Secure Virtual Machine (0x8000000a/eax):
  426. SvmRev: SVM revision = 0x1 (1)
  427. SVM Secure Virtual Machine (0x8000000a/edx):
  428. nested paging = false
  429. LBR virtualization = false
  430. SVM lock = false
  431. NRIP save = false
  432. MSR based TSC rate control = false
  433. VMCB clean bits support = false
  434. flush by ASID = false
  435. decode assists = false
  436. SSSE3/SSE5 opcode set disable = false
  437. pause intercept filter = false
  438. pause filter threshold = false
  439. NASID: number of address space identifiers = 0x10 (16):
  440. (multi-processing synth): none
  441. (multi-processing method): Intel leaf 1/4
  442. (APIC widths synth): CORE_width=0 SMT_width=16
  443. (APIC synth): PKG_ID=65544 CORE_ID=65544 SMT_ID=1
  444. (synth) = Intel Pentium M (Dothan) / Celeron M (Dothan) / Pentium M (Crofton), 90nm
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