module fifo_arbiter(
    input A,
    input B,
    input C,
    input D,
    input CLK,
    output reg [3:0] fifo_take,
    output reg [1:0] ADDR,
    output reg READY
);

reg [3:0] states;
reg states_rst;

initial begin
    states = 0;
    fifo_take <= 0;
    states_rst = 0;
end

always @(posedge CLK)
begin
        if(A || B || C || D)
            begin
            if(A && (~ states[0] || states_rst))
            begin
                READY <= 1;
                ADDR <= 0;
                if(states_rst)
                begin
                    states <= 1;
                    fifo_take <= 1;
                    states_rst <= 0;
                end
                else
                begin
                    states[0] <= 1;
                    fifo_take <= 1;
                end
            end
            else
            begin
                if(B && (~states[1] || states_rst))
                begin
                    READY <= 1;
                    ADDR <= 1;
                    if(states_rst)
                    begin
                        states <= 2;
                        fifo_take <= 2;
                        states_rst <= 0;
                    end
                    else
                    begin
                        states[1] <= 1;
                        fifo_take <= 2;
                    end
                end
                else
                begin
                    if(C && (~states[2] || states_rst))
                    begin
                        READY <= 1;
                        ADDR <= 2;
                        if(states_rst)
                        begin
                            states <= 4;
                            fifo_take <= 4;
                            states_rst <= 0;
                        end
                        else
                        begin
                            states[2] <= 1;
                            fifo_take <= 4;
                        end
                    end
                    else
                    begin
                        if(D && (~states[3] || states_rst))
                        begin
                            READY <= 1;
                            ADDR <= 3;
                            if(states_rst)
                            begin
                                states[3] <= 8;
                                fifo_take <= 8;
                                states_rst <= 0;
                            end
                            else
                            begin
                                states[3] <= 1;
                                fifo_take <= 8;
                            end
                        end
                        else
                        begin
                            READY <= 0;
                            states <= 0;
                            fifo_take <= 0;
                            states_rst <= 0;
                        end
                    end
                end
            end
            if(states == {D, C, B, A} || fifo_take == {D, C, B, A})
            begin
                states_rst <= 1;
            end
        end
        else
        begin
            READY <= 0;
            states <= 0;
            fifo_take <= 0;
            states_rst <= 0;
        end
end

endmodule