lab5 final

module Lab5(
                input [3:0] KEY,
                input signed [7:0] SW,
                output reg [7:0] HEX0,      //7-seg display 0
                output reg [7:0] HEX1,      //7-seg display 0
                output reg [7:0] HEX2,      //7-seg display 0
                output reg [7:0] HEX4,      //7-seg display 0
                output reg [7:0] HEX5,      //7-seg display 0
                output reg [7:0] HEX6       //7-seg display 0
);


    reg signed [7:0] max = -128, min = 127;
    reg unsigned [6:0] max_mg, min_mg;
    wire [7:0] h0,h1,h2,h3;

    hex_7seg s0(max_mg[3:0], h0);
    hex_7seg s1(max_mg[6:4], h1);
    hex_7seg s2(max[7], h2);

    hex_7seg s4(min_mg[3:0], h4);
    hex_7seg s5(min_mg[6:4], h5);
    hex_7seg s6(min[7], h6);


    initial begin
        HEX0 = 7'b1000000;
        HEX1 = 7'b1000000;
        HEX2 = 7'b1000000;
        HEX4 = 7'b1000000;
        HEX5 = 7'b1000000;
        HEX6 = 7'b1000000;

    end

    always @ (negedge KEY[0]) begin
            HEX0 <= h0;
            HEX1 <= h1;
            HEX2 <= h2;
            HEX4 <= h4;
            HEX5 <= h5;
            HEX6 <= h6;

            if(SW < max_mg)
                max_mg = SW;





        end

endmodule


module hex_7seg(hex_digit,seg);
input [3:0] hex_digit;
output [6:0] seg;
reg [6:0] seg;
// seg = {g,f,e,d,c,b,a};
// 0 is on and 1 is off

always @ (hex_digit)
case (hex_digit)
        4'h0: seg = 7'b1000000;
        4'h1: seg = 7'b1111001;     // ---a----
        4'h2: seg = 7'b0100100;     // |      |
        4'h3: seg = 7'b0110000;     // f      b
        4'h4: seg = 7'b0011001;     // |      |
        4'h5: seg = 7'b0010010;     // ---g----
        4'h6: seg = 7'b0000010;     // |      |
        4'h7: seg = 7'b1111000;     // e      c
        4'h8: seg = 7'b0000000;     // |      |
        4'h9: seg = 7'b0011000;     // ---d----
        4'ha: seg = 7'b0001000;
        4'hb: seg = 7'b0000011;
        4'hc: seg = 7'b1000110;
        4'hd: seg = 7'b0100001;
        4'he: seg = 7'b0000110;
        4'hf: seg = 7'b0001110;
endcase
endmodule


module dec_seg7(
                        input [3:0] dec,
                        input carryin,
                        output reg carryout,
                        seg
);
    integer d;
    always @ (dec)
    begin
        d = dec;
        if(carryin) begin
            d = d+1;
        end
        if(dec > 9) begin
            d = d-10;
            carryout = 1;
        end
        case (dec)
        4'h0: seg = 7'b1000000;
        4'h1: seg = 7'b1111001;     // ---a----
        4'h2: seg = 7'b0100100;     // |      |
        4'h3: seg = 7'b0110000;     // f      b
        4'h4: seg = 7'b0011001;     // |      |
        4'h5: seg = 7'b0010010;     // ---g----
        4'h6: seg = 7'b0000010;     // |      |
        4'h7: seg = 7'b1111000;     // e      c
        4'h8: seg = 7'b0000000;     // |      |
        4'h9: seg = 7'b0011000;     // ---d----
    endcase

    end
endmodule