`timescale 1ns / 1ns
//////////////////////////////////////////////////////////////////////////////////
// Company: KU Leuven
// Module Name:  verkeerslicht
// Project Name: verkeerslicht
// Revision 0.01 - File Created
// Additional notes:
//  - Parameter BASE_FREQ is added to speed up simulation
//  - Assumption: 2*FREQ <= BASE_FREQ <= 50000000 (default, Xilinx clock)
//////////////////////////////////////////////////////////////////////////////////
module verkeerslicht(
    input clk,
    input reset,
    input voet,
    input auto,
    output reg hw_g,
    output reg hw_o,
    output reg hw_r,
    output reg zs_g,
    output reg zs_o,
    output reg zs_r
    );
	// Parameter om simulatie te kunnen versnellen
	parameter BASE_FREQ = 50_000_000;  // 50 Mhz Xilinx klok

	// Gereduceerde klokfrequentie (100 Hz) op 'ce' (clock enable).
	// Enkel te gebuiken samen met clk!
	parameter FREQ = 100;
	wire ce;
	prescaler #(.new_freq(FREQ), .old_freq(BASE_FREQ)) maak_ce (clk, reset, ce);

	// Teller voor lichten
	reg [8:0] Q;
   reg       herstart_teller = 1'b0;
   always @(posedge clk, posedge reset) begin
		if (reset)
			Q <= 0;
      else if (ce)
			Q <= herstart_teller? 0: Q + 1;
   end

	// Timing lichten: parameters M_HWG, M_ZSG, M_O, M_R
	// M_* = maximum tellerwaarde voor *
      parameter M_HWG = 400;
		parameter M_ZSG = 200;
		parameter M_O = 100;
		parameter M_R = 100;
	// Definitie toestanden
	// Kies als reset-toestand een veilige toestand (HW en ZS rood),
	// waarbij daarna men zo snel mogelijk naar groen op HW gaat.
      parameter A = 3'b000;
		parameter B = 3'b001;
		parameter C = 3'b010;
		parameter D = 3'b011;
		parameter E = 3'b100;
		parameter F = 3'b101;







      reg [2:0] Current_State;
		reg [2:0] Next_State;
		reg Current_Voet_State;


   // Knop voetgangers
	//   always @(voet or auto)
	//	     if(voet == 1|| auto ==1)
	//			  Voet_State =


	// State register
       always @(posedge clk , posedge reset)
			   begin
				 if(reset)
				    begin
				    Current_State <= A;
					 end
			    else if(ce)
				    Current_State <= Next_State;
			   end

  // Next state logic
	   always @(Current_State , Q)
		  if(herstart_teller == 1)
		     herstart_teller = 0;
		  else
		   case(Current_State)
			  A: if(Q  == M_HWG)
				   begin
				     Next_State <= B;
					  hw_g = 0;
					  hw_o = 1;
					  zs_r = 1;
					  herstart_teller = 1;
				   end
				  else
				    begin
					 Next_State <= A;
					 hw_g = 0;
                hw_o = 0;
                hw_r = 0;
                zs_g = 0;
                zs_o = 0;
                zs_r= 0;

					 hw_g = 1;
					 zs_r = 1;
					 end
			  B : if(Q == M_R)
                begin
                 Next_State <= C;
					  hw_o = 0;
                 hw_r = 1;
					  zs_r = 1;
					  herstart_teller = 1;
                end
          C : if(Q ==M_R)
               begin
                Next_State <= D;
					 hw_r = 0;
					 zs_r = 0;
					 hw_r = 1;
					 zs_g =1;
					 herstart_teller = 1;
               end
         D : if(Q == M_ZSG )
              begin
				  Next_State <= E;
              hw_r = 1;
				  zs_g =0;
				  zs_o = 1;
				  herstart_teller = 1;
              end
        E : if(Q == M_R)
              begin
				  Next_State <= F;
				  hw_r = 1;
              zs_o = 0;
				  zs_r = 1;
				  herstart_teller = 1;
              end
        F : if(Q == 	M_R)
              begin
              Next_State  <= A;
				  hw_r = 0;
				  hw_g = 1;
				  herstart_teller = 1;
              end
		   endcase

  //output logic


endmodule