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- [root]
- type=Root
- children=system
- eventq_index=0
- full_system=false
- sim_quantum=0
- time_sync_enable=false
- time_sync_period=100000000000
- time_sync_spin_threshold=100000000
- [system]
- type=System
- children=clk_domain cpu dvfs_handler membus physmem tlm
- cache_line_size=64
- eventq_index=0
- exit_on_work_items=false
- init_param=0
- kvm_vm=Null
- m5ops_base=4294901760
- mem_mode=timing
- mem_ranges=
- memories=system.physmem
- mmap_using_noreserve=false
- multi_thread=false
- num_work_ids=16
- readfile=
- redirect_paths=
- symbolfile=
- thermal_components=
- thermal_model=Null
- work_begin_ckpt_count=0
- work_begin_cpu_id_exit=-1
- work_begin_exit_count=0
- work_cpus_ckpt_count=0
- work_end_ckpt_count=0
- work_end_exit_count=0
- work_item_id=-1
- workload=Null
- system_port=system.membus.slave[1]
- [system.clk_domain]
- type=SrcClockDomain
- children=voltage_domain
- clock=667
- domain_id=-1
- eventq_index=0
- init_perf_level=0
- voltage_domain=system.clk_domain.voltage_domain
- [system.clk_domain.voltage_domain]
- type=VoltageDomain
- eventq_index=0
- voltage=1.0
- [system.cpu]
- type=TrafficGen
- children=power_state
- clk_domain=system.clk_domain
- config_file=conf/tgen.cfg
- cpu_id=-1
- elastic_req=false
- eventq_index=0
- max_outstanding_reqs=0
- numThreads=1
- power_model=
- power_state=system.cpu.power_state
- progress_check=1000000000
- sids=
- socket_id=0
- ssids=
- stream_gen=none
- system=system
- port=system.membus.slave[0]
- [system.cpu.power_state]
- type=PowerState
- clk_gate_bins=20
- clk_gate_max=1000000000000
- clk_gate_min=1000
- default_state=UNDEFINED
- eventq_index=0
- leaders=
- possible_states=
- [system.dvfs_handler]
- type=DVFSHandler
- domains=
- enable=false
- eventq_index=0
- sys_clk_domain=system.clk_domain
- transition_latency=100000000
- [system.membus]
- type=NoncoherentXBar
- children=power_state
- clk_domain=system.clk_domain
- eventq_index=0
- forward_latency=1
- frontend_latency=2
- power_model=
- power_state=system.membus.power_state
- response_latency=2
- use_default_range=false
- width=16
- master=system.tlm.port
- slave=system.cpu.port system.system_port
- [system.membus.power_state]
- type=PowerState
- clk_gate_bins=20
- clk_gate_max=1000000000000
- clk_gate_min=1000
- default_state=UNDEFINED
- eventq_index=0
- leaders=
- possible_states=
- [system.physmem]
- type=SimpleMemory
- children=power_state
- bandwidth=73.000000
- clk_domain=system.clk_domain
- conf_table_reported=true
- eventq_index=0
- image_file=
- in_addr_map=true
- kvm_map=true
- latency=30000
- latency_var=0
- null=false
- power_model=
- power_state=system.physmem.power_state
- range=0:134217728
- [system.physmem.power_state]
- type=PowerState
- clk_gate_bins=20
- clk_gate_max=1000000000000
- clk_gate_min=1000
- default_state=UNDEFINED
- eventq_index=0
- leaders=
- possible_states=
- [system.tlm]
- type=ExternalSlave
- addr_ranges=0:536870912
- eventq_index=0
- port_data=transactor
- port_type=tlm_slave
- port=system.membus.master[0]
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