`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/21/2020 10:40:27 PM
// Design Name:
// Module Name: main
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module main #(parameter WL = 32, WLinput = 5, WL1 = 32, WL2 = 32, WLcon = 6, WLsign = 16, WLalu = 4)
();

wire clk, rst;
wire [WL-1:0] PC_in;
wire [WL-1:0] result;
wire [((WL1 > WL2 ? WL1+1:WL2+1)-1):0] PCp1F;
wire [WL-1:0] inst;
wire [WL-1:0] instD;
wire [((WL1 > WL2 ? WL1+1:WL2+1)-1):0] PCp1D;
wire [WLinput-1:0] rsD;
wire [WLinput-1:0] rtD;
wire [WLinput-1:0] rdD;
wire [WLcon-1:0] opcoD;
wire [WLcon-1:0] funcD;
wire [25:0] Jaddr;
wire [WLsign-1:0] ImmD;
wire [WLinput-1:0] shamD;
wire [WL-1:0] D1D;
wire [WL-1:0] D2D;
wire [WL-1:0] ALUDMW;
wire RFWED;
wire MtoRFSelD;
wire DMWED;
wire BranchD;
wire [3:0] ALUselD;
wire ALUInSelD;
wire RFDSelD;
wire [WL-1:0] SimmD;
wire [WL-1:0] ALUin1E;
wire [WL-1:0] D2E;
wire [WLinput-1:0] rtE;
wire [WLinput-1:0] rdE;
wire [WL-1:0] SimmE;
//wire [((WL1 > WL2 ? WL1+1:WL2+1)-1):0] PCp1E;
wire [WLinput-1:0] shamE;
wire RFWEE;
wire MtoRFSelE;
wire DMWEE;
wire BranchE;
wire [3:0] ALUselE;
wire ALUInSelE;
wire RFDSelE;
wire [WLinput-1:0] rtdE;
wire [WL-1:0] ALUin2E;
wire [WL-1:0] ALUoutE;
wire [WL-1:0] PCbranchD;
wire [WL-1:0] ALUoutM;
wire [WL-1:0] DMdinM;
wire [WLinput-1:0] rtdM;
//wire [WL-1:0] PCbranchM;
wire RFWEM;
wire MtoRFSelM;
wire DMWEM;
wire BranchM;
wire [3:0] ALUselM;
wire ALUInSelM;
wire RFDSelM;
reg PCselD;
wire [WL-1:0] DMoutM;
wire RFWEW;
wire MtoRFSelW;
wire DMWEW;
wire BranchW;
wire [3:0] ALUselW;
wire ALUInSelW;
wire RFDSelW;
wire [WL-1:0] ALUoutW;
wire [WL-1:0] DMoutW;
wire [WLinput-1:0] rtdW;
wire [WL-1:0] ALUin1D;
wire [WL-1:0] ALUin2D;
wire jump;
wire [WL-1:0] PCjump;
wire [WL-1:0] PC;

wire forwardAD;
wire forwardBD;
reg equalD;
wire [1:0] forwardAE;
wire [1:0] forwardBE;
wire [WL-1:0] ALUin1DE;
wire [WL-1:0] ALUin2DE;
wire flushD;
wire Stall;
reg [WL-1:0] SimmDE;
wire [4:0] rsE;

//initial begin
//PCselD = 0;
//end

assign PCjump = {result[31:26], Jaddr};
//FETCH//
clk clk1(.clk(clk), .rst(rst));
mux #(.WL(WL)) muxPC(.in1(PCp1F), .in2(PCbranchD), .sel(PCselD), .out(PC_in));
mux #(.WL(WL)) mucJump(.in1(PC_in), .in2(PCjump), .sel(jump), .out(PC));
PC #(.WL(WL)) pc1(.clk(clk), .stall(Stall), .PC_input(PC), .PC_result(result));
adder #(.WL1(WL1), .WL2(WL2), .WL0(WL1 > WL2 ? WL1+1:WL2+1)) addy1(.x(result), .y(32'd1), .out(PCp1F));
instruction #( .WL(WL)) instro1(.IMA(result), .instruction(inst));
fetchRegister #(.WL(WL)) fetch(.clk(clk), .stall(Stall), .PCsel(PCselD), .in1(inst), .in2(PCp1F), .out1(instD), .out2(PCp1D));
//FETCH//

assign opcoD = instD[31:26];
assign funcD = instD[5:0];
assign rsD = instD[25:21];
assign rtD = instD[20:16];
assign rdD = instD[15:11];
assign ImmD = instD[15:0];
assign Jaddr = instD[25:0];

//DECODE//
RF_module #(.WL(WL), .WLinput(WLinput)) rf1(.clk(clk), .WE(RFWEW), .rst(rst), .RFRA1(rsD), .RFRA2(rtD), .WA(rtdW), .WD(ALUDMW), .RFRD1(D1D), .RFRD2(D2D));
mux #(.WL(WL)) mux4(.in1(D1D), .in2(ALUoutM), .sel(forwardAD), .out(ALUin1D));//mux
mux #(.WL(WL)) muxy5(.in1(D2D), .in2(ALUoutM), .sel(forwardBD), .out(ALUin2D));//mux
always @(*) begin
if (ALUin1D == ALUin2D) begin
    equalD <= 1'b1;
  end
  else begin
    equalD <= 1'b0;
  end
  end

always @(*) begin
    PCselD <= BranchD & equalD;
 end

control #(.WLcon(WLcon)) con1(.opcode(opcoD), .funct(funcD), .Jump(jump), .RFWE(RFWED), .MtoRFSel(MtoRFSelD), .RFDsel(RFDSelD), .ALUInSel(ALUInSelD), .Branch(BranchD), .ALUsel(ALUselD), .DMWE(DMWED));
HazardUnit danger(.RsD(rsD), .RtD(rtD), .RtE(rtE), .Jump(jump), .RFAE(rtdE), .RFAM(rtdM), .RFAW(rtdW), .stall(Stall), .flush(flushD), .ForwardAD(forwardAD), .ForwardBD(forwardBD), .ForwardAE(forwardAE), .ForwardBE(forwardBE), .RFWEe(RFWEE), .Branchd(BranchD), .MtoRFSele(MtoRFSelE), .RFWEm(RFWEM), .RFWEw(RFWEW), .MtoRFSelm(MtoRFSelM));
SIMM #(.WLsign(WLsign), .WL(WL)) sign1(.unextended(ImmD), .extended(SimmD));

always @(*) begin
    SimmDE <= SimmD << 2;
   end

adder #(.WL1(WL1), .WL2(WL2), .WL0(WL1 > WL2 ? WL1+1:WL2+1)) addy2(.x(SimmDE), .y(PCp1D), .out(PCbranchD));
decodeRegister #(.WL(WL)) decode(.clk(clk), .flush(flushD), .in1(ALUin1D), .in2(ALUin2D), .in3(rtD), .in4(rdD), .in5(SimmD), .in6(rsD), .out1(ALUin1DE), .out2(D2E), .out3(rtE), .out4(rdE), .out5(SimmE), .out6(rsE));
conRegister conD(.clk(clk), .in1(RFWED), .in2(MtoRFSelD), .in3(RFDSelD), .in4(ALUInSelD), .in5(BranchD), .in6(ALUselD), .in7(DMWED), .out1(RFWEE), .out2(MtoRFSelE), .out3(RFDSelE), .out4(ALUInSelE), .out5(BranchE), .out6(ALUselE), .out7(DMWEE));
//DECODE//


//shamt shit
assign shamD = instD[10:6];
shamtRegister shah(.clk(clk), .shamt(shamD), .out(shamE));
//shamt shit


//EXECUTE
//control #(.WLcon(WLcon)) con2(.opcode(opcoD), .funct(funcD), .RFWE(RFWEE), .MtoRFSel(MtoRFSelE), .RFDsel(RFDSelE), .ALUInSel(ALUInSelE), .Branch(BranchE), .ALUsel(ALUselE), .DMWE(DMWEE));
muxitwo #(.WL(WL)) muxy6(.in1(ALUin1DE), .in2(ALUDMW), .in3(ALUoutM), .in4(0), .sel(forwardAE), .out(ALUin1E));
muxitwo #(.WL(WL)) muxy7(.in1(D2E), .in2(ALUDMW), .in3(ALUoutM), .in4(0), .sel(forwardBE), .out(ALUin2DE));
mux #(.WL(WL)) muxy1(.in1(rtE), .in2(rdE), .sel(RFDSelE), .out(rtdE));
mux #(.WL(WL)) muxy2(.in1(ALUin2DE), .in2(SimmE), .sel(ALUInSelE), .out(ALUin2E));
ALU_module #(.WL(WL), .WLalu(WLalu)) alu1(.ALU_in1(ALUin1E), .ALU_in2(ALUin2E), .ALU_sel(ALUselE), .shamt(shamD), .ALU_out(ALUoutE));

execRegister #(.WL(WL)) execute(.clk(clk), .in2(ALUoutE), .in3(ALUin2DE), .in4(rtdE), .out2(ALUoutM), .out3(DMdinM), .out4(rtdM));
conRegister conE(.clk(clk), .in1(RFWEE), .in2(MtoRFSelE), .in3(RFDSelE), .in4(ALUInSelE), .in5(BranchE), .in6(ALUselE), .in7(DMWEE), .out1(RFWEM), .out2(MtoRFSelM), .out3(RFDSelM), .out4(ALUInSelM), .out5(BranchM), .out6(ALUselM), .out7(DMWEM));
//EXECUTE


//MEMORY
data #(.WL(WL)) data1(.clk(clk), .DMWD(DMdinM), .DMWE(DMWEM), .DMA(ALUoutM), .DMRD(DMoutM));
memRegister #(.WL(WL)) memory(.clk(clk), .in1(ALUoutM), .in2(DMoutM), .in3(rtdM), .out1(ALUoutW), .out2(DMoutW), .out3(rtdW));
conRegister conM(.clk(clk), .in1(RFWEM), .in2(MtoRFSelM), .in3(RFDSelM), .in4(ALUInSelM), .in5(BranchE), .in6(ALUselM), .in7(DMWEM), .out1(RFWEW), .out2(MtoRFSelW), .out3(RFDSelW), .out4(ALUInSelW), .out5(BranchW), .out6(ALUselW), .out7(DMWEW));
//MEMORY


//WRITEBACK
mux #(.WL(WL)) muxy3(.in1(ALUoutW), .in2(DMoutW), .sel(MtoRFSelW), .out(ALUDMW));
//WRITEBACK

endmodule