MIPS Fetch

module fetch(clk, PC_src, immediate, instru, new_pc);
    input clk, PC_src, immediate;
    output instru, new_pc;

    //input
    wire clk, PC_src;
    wire[31:0] immediate;

    //output
    reg[31:0] instru, new_pc;

    //internal
    reg[31:0] pc, instru_mem[14:0];
    integer i;


    initial begin
        pc = -4;
        i = 0;

        for(i = 0; i < 15; i = i + 1) begin
            instru_mem[i] = 0;
        end
    end

    always@(posedge clk) begin
        if(PC_src == 1) begin
            pc = immediate;
        end else begin
            pc = pc + 4;
        end
    end

    always@(negedge clk) begin
        new_pc = pc;
        instru = instru_mem[pc];
    end
endmodule