/*cache finite state machine*/
timeunit 1ns;
timeprecision 1ps;
import cache_def::*;

`define TB_CLK_PERIOD 4

module cache_simple_tb();

bit              clk;
bit              rst;
cpu_req_type     cpu_req; //CPU request input (CPU->cache)
mem_data_type    mem_data; //memory response (memory->cache)
mem_req_type     mem_req; //memory request (cache->memory)
cpu_result_type  cpu_res; //cache result (cache->CPU)

dm_cache_fsm dut (.*);

/////////////////////////////
// Clock and reset signals //
/////////////////////////////
initial begin
  clk = 0;
  forever clk = #(`TB_CLK_PERIOD/2) !clk;
end

initial begin
  rst   = 1;
  repeat (10)  @(posedge clk);
  rst   = 0;
end

initial begin
  repeat (20)  @(posedge clk);
  cpu_req.addr  = 32'h1234FF66;
  cpu_req.data  = 32'h77777777;
  cpu_req.rw    = 1'b1;
  cpu_req.valid = 1'b1;
  repeat (10)  @(posedge clk);
  cpu_req.addr  = 32'h000;
  cpu_req.data  = 32'h1234FF66;
  cpu_req.rw    = 1'b1;
  cpu_req.valid = 1'b1;
end

initial begin
  repeat (20)  @(posedge clk);
  mem_data.ready = 1;
  mem_data.data  = 128'h1234FF66;
  repeat (20)  @(posedge clk);
  mem_data.ready = 0;
  mem_data.data  = 0;
end

endmodule : cache_simple_tb