myuart1

INCLUDE "lpm_counter.inc";
INCLUDE "majority.inc";
INCLUDE "myshiftreg.inc";

SUBDESIGN uart_1
(
in_data, clk : INPUT;
res[7..0], my_par : OUTPUT;
)
VARIABLE
FSM: MACHINE
WITH STATES (silence, start, read, parity, stop);
pr_bit: DFF; %previous bit%
count_read : lpm_counter WITH (LPM_WIDTH = 4); %ñ÷¸ò÷èê ÷àñòîòû; ÷èñëî áèòîâ â ñ÷¸òå(ðàçìåðíîñòü q[]) - 4%
count_vol : lpm_counter WITH (LPM_WIDTH = 3); %ñ÷¸ò÷èê îáúåìà èíôîðìàöèè; ÷èñëî áèòîâ â ñ÷¸òå - 3%
mj_sc : majority;
reg : myshiftreg; %êîëè÷åñòâî òðèããåðîâ - 8%
par : DFFE; %parity%
cen : NODE; %ôëàæîê äëÿ ñ÷¸ò÷èêà%

BEGIN
FSM.clk = clk;
count_read.clock = clk;
count_vol.clock = clk;
count_read.cnt_en = cen; %cnt_en îòêëþ÷àåò ñ÷¸ò÷èê ïðè = 0%
pr_bit.clk = clk;
reg.clk = clk;
mj_sc.clk = clk;
par.clk = clk;
my_par = par.q;
res[] = reg.q[];

CASE fsm IS
    WHEN silence =>
        count_read.sclr = GND; %sclr îòâå÷àåò çà î÷èñòêó ñ÷¸ò÷èêà íà ñëåäóþùåì àêòèâíîì ôðîíòå òàêòà%
        IF ((pr_bit.q == VCC) & (in_data == GND)) THEN %åñëè âñòðåòèëè ìîë÷àíèå ïåðåä ñòàðòîâûì áèòîì, òî ïåðåõîäèì íà ñîñòîÿíèå ñòàðòà%
            cen = VCC;
            pr_bit.d = in_data;
            fsm = start;
        ELSE
            pr_bit.d = in_data;
            cen = GND;
        END IF;
    WHEN start =>
        count_read.cnt_en = VCC; %èçìåíÿåì ôëàæîê%
        count_vol.sclr = VCC;
        IF (count_read.q[] == 9) THEN
            IF (in_data == VCC) THEN
                fsm = read;
            ELSE
                fsm = silence;
                count_read.sclr = VCC;
            END IF;
        END IF;
    WHEN read =>
        count_read.cnt_en = VCC;
        count_vol.sclr = GND;
        %íåîáõîäèìî ïðîâåðèòü äàííûå ñ ïîìîùüþ ìàæîð. ñõåìû: ïðèìåðíî â ñåðåäèíå êàæäîãî âõîäíîãî òàêòà ïðîèñõîäèò 3 ñ÷èòûâàíèå è èõ ñîîòâ. ñðàâíåíèå%
        IF (count_read.q[] == 7) THEN
            mj_sc.sel[] = 0;
            mj_sc.data0 = in_data;
        ELSE
            IF (count_read.q[] == 8) THEN
                mj_sc.sel[] = 1;
                mj_sc.data1 = in_data;
            ELSE
                IF (count_read.q[] == 9) THEN
                    mj_sc.sel[] = 2;
                    mj_sc.data2 = in_data;
                    reg.load = VCC;
                    reg.data = mj_sc.q;
                    IF (count_vol.q[] == 7) THEN
                        fsm = parity;
                    ELSE
                        count_vol.cnt_en = VCC;
                    END IF;

                ELSE
                    reg.load = GND; % load ïðè 0 îòâå÷àåò çà àêòèâàöèþ ñäâèãà; 1 - load operation %
                    count_vol.cnt_en = GND;
                END IF;
            END IF;
        END IF;
    WHEN parity =>
        count_read.cnt_en = VCC;
        reg.load = GND;
        IF (count_read.q[] == 8) THEN
            par.d = in_data;
            par.ena = VCC;
            fsm = stop;
        END IF;
    WHEN stop =>
        par.ena = GND;
        count_read.cnt_en = VCC;
        IF (count_read.q[] == 8) THEN
            fsm = silence;
            pr_bit.d = in_data;
            count_vol.sclr = VCC;
            count_read.sclr = VCC;
            cen = GND;
        END IF;
    END CASE;
END;