`timescale 1ns / 1ps
module rategen(
    input  clk,rst,
    output ce
    );
    //Generate 1 clock wide pulse on output CY
reg [25:0] Q;

always @(posedge clk)
begin
   if (rst | ce)
      Q <= 0;
   else
      Q <= Q + 1;
end

assign ce = (Q == 49999999); //ELVILEG Másodpercre jó:
//assign ce = (Q == 2); //tesztre

endmodule