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- module mac #(parameter S_WIDTH=4, W_WIDTH=4, MULT_WIDTH = 8, ACC_PR_WIDTH = 10, ACC_WIDTH = 6) (in1, in2, clk, reset, acc);
- input signed [S_WIDTH-1:0] in1;
- input signed [W_WIDTH-1:0] in2;
- input clk;
- output reg signed [ACC_WIDTH-1:0] acc;
- input reset;
- reg signed [MULT_WIDTH-1:0] out_mult;
- reg signed [ACC_PR_WIDTH:0] acc_pre_reduced;
- always @(posedge clk or posedge reset)
- begin
- out_mult <= in1*in2;
- if (reset)
- begin
- acc_pre_reduced <= 0;
- acc <= 0;
- end
- else
- acc_pre_reduced = out_mult+acc_pre_reduced;
- if (acc_pre_reduced > 2**(ACC_WIDTH-1)) acc = 2**(ACC_WIDTH-1)-1;
- else if (acc_pre_reduced < -(2**(ACC_WIDTH-1))) acc = -2**(ACC_WIDTH-1);
- else acc = acc_pre_reduced;
- end
- endmodule
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