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  1. Broadcom VMCS log file
  2. Created 14-May-12 19:44:15
  3. MESS: 00:00:00.617047:0: /dts-v1/;
  4. MESS: 00:00:00.617065:0: // magic: 0xd00dfeed
  5. MESS: 00:00:00.617086:0: // totalsize: 0xd97 (3479)
  6. MESS: 00:00:00.617103:0: // off_dt_struct: 0x38
  7. MESS: 00:00:00.617120:0: // off_dt_strings: 0xc5c
  8. MESS: 00:00:00.617137:0: // off_mem_rsvmap: 0x28
  9. MESS: 00:00:00.617153:0: // version: 17
  10. MESS: 00:00:00.617170:0: // last_comp_version: 16
  11. MESS: 00:00:00.617187:0: // boot_cpuid_phys: 0x0
  12. MESS: 00:00:00.617205:0: // size_dt_strings: 0x13b
  13. MESS: 00:00:00.617221:0: // size_dt_struct: 0xc24
  14. MESS: 00:00:00.617231:0:
  15. MESS: 00:00:00.617245:0: / {
  16. MESS: 00:00:00.617288:0: #address-cells = <0x00000001>;
  17. MESS: 00:00:00.617326:0: #size-cells = <0x00000001>;
  18. MESS: 00:00:00.617354:0: model = "BCM2835";
  19. MESS: 00:00:00.617802:0: compatible = [62 72 6f 61 64 63 6f 6d 2c 62 63 6d 32 38 33 35 00 62 72 6f 61 64 63 6f 6d 2c 62 63 6d 32 37 30 38 00];
  20. MESS: 00:00:00.617821:0: chosen {
  21. MESS: 00:00:00.617832:0: };
  22. MESS: 00:00:00.617848:0: aliases {
  23. MESS: 00:00:00.617861:0: };
  24. MESS: 00:00:00.617878:0: memory {
  25. MESS: 00:00:00.617910:0: device_type = "memory";
  26. MESS: 00:00:00.617958:0: reg = <0x00000000 0x00000000>;
  27. MESS: 00:00:00.617970:0: };
  28. MESS: 00:00:00.617986:0: cpus {
  29. MESS: 00:00:00.618002:0: cpu@0 {
  30. MESS: 00:00:00.618037:0: compatible = "arm,1176jz-f";
  31. MESS: 00:00:00.618051:0: };
  32. MESS: 00:00:00.618064:0: };
  33. MESS: 00:00:00.618081:0: display {
  34. MESS: 00:00:00.618119:0: compatible = "broadcom,bcm2708-fb";
  35. MESS: 00:00:00.618162:0: #address-cells = <0x00000000>;
  36. MESS: 00:00:00.618204:0: #size-cells = <0x00000000>;
  37. MESS: 00:00:00.618218:0: };
  38. MESS: 00:00:00.618237:0: axi@0x20000000 {
  39. MESS: 00:00:00.618269:0: compatible = "simple-bus";
  40. MESS: 00:00:00.618311:0: #address-cells = <0x00000001>;
  41. MESS: 00:00:00.618352:0: #size-cells = <0x00000001>;
  42. MESS: 00:00:00.618399:0: reg = <0x20000000 0x01000000>;
  43. MESS: 00:00:00.618464:0: ranges = <0x00000000 0x20000000 0x01000000>;
  44. MESS: 00:00:00.618484:0: st@0x3000 {
  45. MESS: 00:00:00.618518:0: compatible = "simple-bus";
  46. MESS: 00:00:00.618562:0: #address-cells = <0x00000001>;
  47. MESS: 00:00:00.618605:0: #size-cells = <0x00000001>;
  48. MESS: 00:00:00.618655:0: reg = <0x00003000 0x00001000>;
  49. MESS: 00:00:00.618723:0: ranges = <0x00000000 0x00003000 0x00001000>;
  50. MESS: 00:00:00.618743:0: stc@0x004 {
  51. MESS: 00:00:00.619036:0: compatible = [6d 6d 69 6f 2d 63 6c 6f 63 6b 00 73 69 6d 70 6c 65 2d 62 75 73 00];
  52. MESS: 00:00:00.619083:0: #address-cells = <0x00000001>;
  53. MESS: 00:00:00.619129:0: #size-cells = <0x00000001>;
  54. MESS: 00:00:00.619212:0: reg = <0x00000004 0x00000004 0x00000000 0x00000004>;
  55. MESS: 00:00:00.619234:0: ranges;
  56. MESS: 00:00:00.619267:0: clock-outputs = "sys";
  57. MESS: 00:00:00.619317:0: clock-frequency = <0x000f4240>;
  58. MESS: 00:00:00.619360:0: rating = <0x0000012c>;
  59. MESS: 00:00:00.619380:0: timer0@0x00c {
  60. MESS: 00:00:00.619416:0: compatible = "mmio-timer";
  61. MESS: 00:00:00.619472:0: reg = <0x0000000c 0x00000004>;
  62. MESS: 00:00:00.619521:0: interrupt-parent = <0x00000001>;
  63. MESS: 00:00:00.619568:0: interrupts = <0x00000000>;
  64. MESS: 00:00:00.619612:0: index = <0x00000000>;
  65. MESS: 00:00:00.619655:0: rating = <0x00000000>;
  66. MESS: 00:00:00.619702:0: min-delta = <0x0000000f>;
  67. MESS: 00:00:00.619718:0: };
  68. MESS: 00:00:00.619737:0: timer1@0x010 {
  69. MESS: 00:00:00.619774:0: compatible = "mmio-timer";
  70. MESS: 00:00:00.619829:0: reg = <0x00000010 0x00000004>;
  71. MESS: 00:00:00.619879:0: interrupt-parent = <0x00000001>;
  72. MESS: 00:00:00.619925:0: interrupts = <0x00000001>;
  73. MESS: 00:00:00.619967:0: index = <0x00000001>;
  74. MESS: 00:00:00.620012:0: rating = <0x000000c8>;
  75. MESS: 00:00:00.620059:0: min-delta = <0x0000000f>;
  76. MESS: 00:00:00.620074:0: };
  77. MESS: 00:00:00.620095:0: timer2@0x014 {
  78. MESS: 00:00:00.620131:0: compatible = "mmio-timer";
  79. MESS: 00:00:00.620187:0: reg = <0x00000014 0x00000004>;
  80. MESS: 00:00:00.620236:0: interrupt-parent = <0x00000001>;
  81. MESS: 00:00:00.620283:0: interrupts = <0x00000002>;
  82. MESS: 00:00:00.620326:0: index = <0x00000002>;
  83. MESS: 00:00:00.620370:0: rating = <0x00000000>;
  84. MESS: 00:00:00.620417:0: min-delta = <0x0000000f>;
  85. MESS: 00:00:00.620432:0: };
  86. MESS: 00:00:00.620452:0: timer3@0x018 {
  87. MESS: 00:00:00.620489:0: compatible = "mmio-timer";
  88. MESS: 00:00:00.620544:0: reg = <0x00000018 0x00000004>;
  89. MESS: 00:00:00.620594:0: interrupt-parent = <0x00000001>;
  90. MESS: 00:00:00.620640:0: interrupts = <0x00000003>;
  91. MESS: 00:00:00.620682:0: index = <0x00000003>;
  92. MESS: 00:00:00.620726:0: rating = <0x0000012c>;
  93. MESS: 00:00:00.620773:0: min-delta = <0x0000000f>;
  94. MESS: 00:00:00.620789:0: };
  95. MESS: 00:00:00.620802:0: };
  96. MESS: 00:00:00.620814:0: };
  97. MESS: 00:00:00.620834:0: armctrl@0xB000 {
  98. MESS: 00:00:00.620867:0: compatible = "simple-bus";
  99. MESS: 00:00:00.620911:0: #address-cells = <0x00000001>;
  100. MESS: 00:00:00.620955:0: #size-cells = <0x00000001>;
  101. MESS: 00:00:00.621005:0: reg = <0x0000b000 0x00001000>;
  102. MESS: 00:00:00.621073:0: ranges = <0x00000000 0x0000b000 0x00001000>;
  103. MESS: 00:00:00.621106:0: intc@0x200 {
  104. MESS: 00:00:00.621143:0: compatible = "simple-bus";
  105. MESS: 00:00:00.621191:0: #address-cells = <0x00000001>;
  106. MESS: 00:00:00.621237:0: #size-cells = <0x00000001>;
  107. MESS: 00:00:00.621291:0: reg = <0x00000200 0x00000200>;
  108. MESS: 00:00:00.621360:0: ranges = <0x00000000 0x00000200 0x00000200>;
  109. MESS: 00:00:00.621381:0: bank0@0x000 {
  110. MESS: 00:00:00.621427:0: compatible = "broadcom,bcm2708-armctrl-ic";
  111. MESS: 00:00:00.621548:0: reg = <0x00000000 0x00000004 0x00000018 0x00000004 0x00000024 0x00000004>;
  112. MESS: 00:00:00.621576:0: interrupt-controller;
  113. MESS: 00:00:00.621626:0: #interrupt-cells = <0x00000001>;
  114. MESS: 00:00:00.621677:0: interrupt-base = <0x00000040>;
  115. MESS: 00:00:00.621726:0: source-mask = <0x000000ff>;
  116. MESS: 00:00:00.621773:0: bank-mask = <0x00000300>;
  117. MESS: 00:00:00.621823:0: shortcut-mask = <0x001ffc00>;
  118. MESS: 00:00:00.622394:0: shortcut-map = <0x00000008 0x00000007 0x00000008 0x00000009 0x00000008 0x0000000a 0x00000008 0x00000012 0x00000008 0x00000013 0x00000009 0x00000015 0x00000009 0x00000016 0x00000009 0x00000017 0x00000009 0x00000018 0x00000009 0x00000019 0x00000009 0x0000001e>;
  119. MESS: 00:00:00.622443:0: linux,phandle = <0x00000002>;
  120. MESS: 00:00:00.622489:0: phandle = <0x00000002>;
  121. MESS: 00:00:00.622502:0: };
  122. MESS: 00:00:00.622524:0: bank1@0x004 {
  123. MESS: 00:00:00.622570:0: compatible = "broadcom,bcm2708-armctrl-ic";
  124. MESS: 00:00:00.622690:0: reg = <0x00000004 0x00000004 0x00000010 0x00000004 0x0000001c 0x00000004>;
  125. MESS: 00:00:00.622742:0: interrupt-parent = <0x00000002>;
  126. MESS: 00:00:00.622770:0: interrupt-controller;
  127. MESS: 00:00:00.622822:0: #interrupt-cells = <0x00000001>;
  128. MESS: 00:00:00.622870:0: #address-cells = <0x00000000>;
  129. MESS: 00:00:00.622918:0: bank-interrupt = <0x00000008>;
  130. MESS: 00:00:00.622968:0: interrupt-base = <0x00000000>;
  131. MESS: 00:00:00.623015:0: source-mask = <0xffffffff>;
  132. MESS: 00:00:00.623063:0: linux,phandle = <0x00000001>;
  133. MESS: 00:00:00.623109:0: phandle = <0x00000001>;
  134. MESS: 00:00:00.623123:0: };
  135. MESS: 00:00:00.623145:0: bank2@0x008 {
  136. MESS: 00:00:00.623191:0: compatible = "broadcom,bcm2708-armctrl-ic";
  137. MESS: 00:00:00.623310:0: reg = <0x00000008 0x00000004 0x00000014 0x00000004 0x00000020 0x00000004>;
  138. MESS: 00:00:00.623362:0: interrupt-parent = <0x00000002>;
  139. MESS: 00:00:00.623390:0: interrupt-controller;
  140. MESS: 00:00:00.623442:0: #interrupt-cells = <0x00000001>;
  141. MESS: 00:00:00.623491:0: #address-cells = <0x00000000>;
  142. MESS: 00:00:00.623541:0: bank-interrupt = <0x00000009>;
  143. MESS: 00:00:00.623589:0: interrupt-base = <0x00000020>;
  144. MESS: 00:00:00.623637:0: source-mask = <0xffffffff>;
  145. MESS: 00:00:00.623685:0: linux,phandle = <0x00000003>;
  146. MESS: 00:00:00.623731:0: phandle = <0x00000003>;
  147. MESS: 00:00:00.623744:0: };
  148. MESS: 00:00:00.623765:0: fiq@0x00c {
  149. MESS: 00:00:00.623814:0: compatible = "broadcom,bcm2708-armctrl-ic-fiq";
  150. MESS: 00:00:00.623868:0: reg = <0x0000000c 0x00000004>;
  151. MESS: 00:00:00.623919:0: interrupt-parent = <0x00000002>;
  152. MESS: 00:00:00.623947:0: interrupt-controller;
  153. MESS: 00:00:00.623999:0: #interrupt-cells = <0x00000000>;
  154. MESS: 00:00:00.624071:0: banks = <0x00000008 0x00000009 0x00000000>;
  155. MESS: 00:00:00.624086:0: };
  156. MESS: 00:00:00.624101:0: };
  157. MESS: 00:00:00.624122:0: armtimer@0x400 {
  158. MESS: 00:00:00.624158:0: compatible = "arm,sp804";
  159. MESS: 00:00:00.624212:0: reg = <0x00000400 0x00000024>;
  160. MESS: 00:00:00.624260:0: interrupt-parent = <0x00000002>;
  161. MESS: 00:00:00.624304:0: interrupts = <0x00000000>;
  162. MESS: 00:00:00.624317:0: };
  163. MESS: 00:00:00.624337:0: mbox0@0x880 {
  164. MESS: 00:00:00.624377:0: compatible = "broadcom,bcm2708-mbox";
  165. MESS: 00:00:00.624432:0: reg = <0x00000880 0x00000040>;
  166. MESS: 00:00:00.624480:0: interrupt-parent = <0x00000002>;
  167. MESS: 00:00:00.624524:0: interrupts = <0x00000001>;
  168. MESS: 00:00:00.624552:0: access = "rw";
  169. MESS: 00:00:00.624623:0: channels = <0x00000000 0x00000001 0x00000003>;
  170. MESS: 00:00:00.624823:0: channel-names = [70 6f 77 65 72 00 66 62 00 76 63 68 69 71 00];
  171. MESS: 00:00:00.624837:0: };
  172. MESS: 00:00:00.624851:0: };
  173. MESS: 00:00:00.624873:0: watchdog@0x100000 {
  174. MESS: 00:00:00.624915:0: compatible = "broadcom,bcm2708-pm-wdog";
  175. MESS: 00:00:00.624965:0: reg = <0x00100000 0x00001000>;
  176. MESS: 00:00:00.624977:0: };
  177. MESS: 00:00:00.624993:0: amba {
  178. MESS: 00:00:00.625028:0: compatible = "arm,amba-bus";
  179. MESS: 00:00:00.625072:0: #address-cells = <0x00000001>;
  180. MESS: 00:00:00.625116:0: #size-cells = <0x00000001>;
  181. MESS: 00:00:00.625134:0: ranges;
  182. MESS: 00:00:00.625156:0: uart0@0x201000 {
  183. MESS: 00:00:00.625280:0: compatible = <0x61726d2c 0x706c3031 0x31006172 0x6d2c7072 0x696d6563 0x656c6c00>;
  184. MESS: 00:00:00.625335:0: reg = <0x00201000 0x00001000>;
  185. MESS: 00:00:00.625383:0: interrupt-parent = <0x00000003>;
  186. MESS: 00:00:00.625430:0: interrupts = <0x00000019>;
  187. MESS: 00:00:00.625445:0: };
  188. MESS: 00:00:00.625458:0: };
  189. MESS: 00:00:00.625471:0: };
  190. MESS: 00:00:00.625483:0: };
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