module sertopar(clk, nrst, en, valid_in, data_in, data_out, valid_out);

    input   clk, nrst, en, valid_in, data_in;
    output  [3:0] data_out;
    output  valid_out;
    wire    x0,x1,x2,x3,x4,q0,q1,q2,q3,q4;

    //  Serial to Parallel

    assign  x0 = en ? data_in : q0;
    dff     dff0(clk, nrst, x0, q0);

    assign  x1 = valid_in ? q0 : q1;
    assign  data_out[0] = x1;
    dff dff1(clk, nrst, x1, q1);

    assign  x2 = valid_in ? q1 : q2;
    assign  data_out[1] = x2;
    dff dff2(clk, nrst, x2, q2);

    assign  x3 = valid_in ? q2 : q3;
    assign  data_out[2] = x3;
    dff dff3(clk, nrst, x3, q3);

    assign  x4 = valid_in ? q3 : q4;
    assign  data_out[3] = x4;
    dff dff4(clk, nrst, x4, q4);

    //  Valid out checker




endmodule