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DNALock ise report

rezafara Oct 17th, 2015 176 Never
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  1.  
  2. Started : "Synthesize - XST".
  3. Running xst...
  4. Command Line: xst -intstyle ise -ifn "C:/Projects/Anti clone S6/code/test1/DNATest/testDNALock.xst" -ofn "C:/Projects/Anti clone S6/code/test1/DNATest/testDNALock.syr"
  5. Reading design: testDNALock.prj
  6.  
  7. =========================================================================
  8. *                          HDL Parsing                                  *
  9. =========================================================================
  10. Parsing VHDL file "C:\Projects\Anti clone S6\code\test1\DNATest\IOCutOut.vhd" into library work
  11. Parsing entity <IOCutOut>.
  12. Parsing architecture <Behavioral> of entity <iocutout>.
  13. WARNING:HDLCompiler:1369 - "C:\Projects\Anti clone S6\code\test1\DNATest\IOCutOut.vhd" Line 66: Possible infinite loop; process does not have a wait statement
  14. Parsing VHDL file "C:\Projects\Anti clone S6\code\test1\DNATest\DNALock.vhd" into library work
  15. Parsing entity <DNALock>.
  16. INFO:HDLCompiler:1676 - "C:\Projects\Anti clone S6\code\test1\DNATest\DNALock.vhd" Line 36. declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output
  17. Parsing architecture <Behavioral> of entity <dnalock>.
  18. Parsing VHDL file "C:\Projects\Anti clone S6\code\test1\DNATest\testDNALock.vhd" into library work
  19. Parsing entity <testDNALock>.
  20. INFO:HDLCompiler:1676 - "C:\Projects\Anti clone S6\code\test1\DNATest\testDNALock.vhd" Line 53. declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output
  21. Parsing architecture <Behavioral> of entity <testdnalock>.
  22. INFO:HDLCompiler:1676 - "C:\Projects\Anti clone S6\code\test1\DNATest\testDNALock.vhd" Line 99. declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output
  23.  
  24. =========================================================================
  25. *                            HDL Elaboration                            *
  26. =========================================================================
  27.  
  28. Elaborating entity <testDNALock> (architecture <Behavioral>) from library <work>.
  29.  
  30. Elaborating entity <DNALock> (architecture <Behavioral>) from library <work>.
  31. WARNING:HDLCompiler:1127 - "C:\Projects\Anti clone S6\code\test1\DNATest\DNALock.vhd" Line 71: Assignment to sr_readb ignored, since the identifier is never used
  32. WARNING:HDLCompiler:92 - "C:\Projects\Anti clone S6\code\test1\DNATest\DNALock.vhd" Line 162: dna_clk_temp should be on the sensitivity list of the process
  33. WARNING:HDLCompiler:1127 - "C:\Projects\Anti clone S6\code\test1\DNATest\DNALock.vhd" Line 145: Assignment to sr_clk ignored, since the identifier is never used
  34. WARNING:HDLCompiler:92 - "C:\Projects\Anti clone S6\code\test1\DNATest\DNALock.vhd" Line 201: sr_out should be on the sensitivity list of the process
  35.  
  36. Elaborating entity <IOCutOut> (architecture <Behavioral>) from library <work>.
  37.  
  38. =========================================================================
  39. *                           HDL Synthesis                               *
  40. =========================================================================
  41.  
  42. Synthesizing Unit <testDNALock>.
  43.     Related source file is "C:\Projects\Anti clone S6\code\test1\DNATest\testDNALock.vhd".
  44. WARNING:Xst:647 - Input <CLK_98MHz> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
  45. WARNING:Xst:2935 - Signal 'DNAVerify', unconnected in block 'testDNALock', is tied to its initial value (0).
  46.     Summary:
  47.         no macro.
  48. Unit <testDNALock> synthesized.
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