Projeto Final

module projeto_final(CLOCK_50, KEY, SW, HEX0, HEX1, HEX2, HEX3, LEDR, LEDG, co_soma1, soma1, co_soma_1, co_soma_2, soma2, co_soma_2, co_soma_3, soma3, sub_1, bo_sub_1, sub_2, bo_sub_2, sub_3, bo_sub_3);

reg [2:0] mem [0:3];

input [9:0] SW;
output [6:0]HEX0;
output [6:0]HEX1;
output [6:0]HEX2;
output [6:0]HEX3;
output reg [9:0]LEDR;
output reg [7:0]LEDG;
input CLOCK_50;
input [3:0]KEY;

output wire co_soma1, soma1, co_soma_1, co_soma_2, soma2, co_soma_2, co_soma_3, soma3, sub_1, bo_sub_1, sub_2, bo_sub_2, sub_3, bo_sub_3;

assign data_1 = {SW[5], SW[4], SW[3]};
assign data_2 = {SW[9], SW[8], SW[7]};

reg[31:0] cont;
reg counter;
assign clear = ~KEY[0];

reg [4:0]temp;
reg salvar = 0;

hex_7seg_operation(LEDR[9:6],HEX3);
hex_7seg(LEDR[4:0], HEX0, HEX1, HEX2, LEDR[4], LEDR[2], LEDR[1], LEDR[0]);

F_A f_a0(SW[3], SW[7], SW[6], co_soma_1 , soma1);
F_A f_a1(SW[4], SW[8], co_soma_1, co_soma_2 , soma2);
F_A f_a2(SW[5], SW[9], co_soma_2, co_soma_3 , soma3);

F_S f_s0(SW[7], SW[3], SW[6], sub_1, bo_sub_1);
F_S f_s1(SW[8], SW[4], bo_sub_1, sub_2, bo_sub_2);
F_S f_s2(SW[9], SW[5], bo_sub_2, sub_3, bo_sub_3);

always @(negedge CLOCK_50) // Divisao de clock
begin
 if (clear)
    cont = 0;
 else begin
    cont = cont + 1;
    counter = cont[23]; // (50*10^6) / (2^23) = 5,9
 end

end

always @ (negedge counter)
begin
    //Onde vai acontecer as coisas

    if (SW[2] == 0 && SW[1] == 0 && SW[0] == 0) begin //0 - Nada
        LEDR[9:6] = 4'b0000; // Display 4
        LEDR[4:0] = 5'b10000; // flag, blank1, blank2, blank3

    end else if (SW[2] == 0 && SW[1] == 0 && SW[0] == 1) begin //1 - Soma
        LEDR[9:6] = 4'b0001;
        LEDR[4] = 1'b0;
        LEDR[3:0] = {co_soma_3, soma3, soma2, soma1};

    end else if (SW[2] == 0 && SW[1] == 1 && SW[0] == 0) begin //2 - Subtração
        LEDR[9:6] = 4'b0010;
        LEDR[4] = 1'b0;
        LEDR[3:0] = {bo_sub_3, sub_3, sub_2, sub_1};

    end else if (SW[2] == 0 && SW[1] == 1 && SW[0] == 1) begin //3 - Inversao
        LEDR[9:6] = 4'b0011;
        LEDR[4] = 5'b1;
        LEDR[2:0] = {~SW[9], ~SW[8], ~SW[7]};

        //Falta implementar numeros negativos, se der tempo a gente faz
    end else if (SW[2] == 1 && SW[1] == 1 && SW[0] == 0) begin //6 - Deslocamento direita
        LEDR[9:6] = 4'b0110;
        LEDR[4] = 1'b1;
        if (KEY[2] == 0) begin
            LEDR[2:0] = {SW[9], SW[8], SW[7]};
        end
        else if (KEY[3] == 0) begin
            LEDR[2:0] = LEDR[2:0] >> 1;
        end

    end else if (SW[2] == 1 && SW[1] == 1 && SW[0] == 1) begin //7 - Deslocamento Esquerda
        LEDR[9:6] = 4'b0111;
        LEDR[4] = 1'b1;
        if (KEY[2] == 0)
        LEDR[2:0] = {SW[9], SW[8], SW[7]};
        if (KEY[3] == 0) begin
            LEDR[2:0] = LEDR[2:0] << 1;
        end

    end else if (SW[2] == 1 && SW[1] == 0 && SW[0] == 0) begin //4 - Escrita na memória
        LEDR[9:6] = 4'b0100;
        LEDR[4:3] = 1'b0;
        LEDR[2:0] = SW[9:7];
        if (SW[5] != 1'b0 || SW[4] != 1'b0 || SW[3] != 1'b0) begin
            LEDG[3] = 0;
            LEDG[2:0] = {SW[5], SW[4], SW[3]};
        end
        if (KEY[3] == 0) begin
            mem[SW[9:7]] = LEDG[3:0];
            LEDG[3:0] = 4'b0;
            salvar = ~salvar;
        end
    end else if (SW[2] == 1 && SW[1] == 0 && SW[0] == 1) begin //5 - Leitura da memória
        LEDR[9:6] = 4'b0101;
        LEDR[4:3] = 1'b0;
        LEDG[7:4] = mem[SW[9:7]];
        LEDR[3:0] = LEDG[7:4];
    end

    if (KEY[1] == 0) begin // Salvar temporariamente
        if (salvar == 0)
            LEDG[4:0] = LEDR[4:0];
        else
            LEDG[4:0] = 5'b0;
        salvar = ~salvar;
    end
end

endmodule

//-----------------------------------------DISPLAY 3, 2, 1-----------------------------------------------------------
//hex_7seg(LEDR[4:0], HEX0, HEX1, HEX2);
module hex_7seg(hex_digit, seg, seg2, seg3, flag, blank_1, blank_2, blank_3);
    input [4:0]hex_digit;
    input blank_1, blank_2, blank_3, flag;
    reg [3:0]div;
    reg [3:0]resto;
    output reg [6:0]seg;
    output reg [6:0]seg2;
    output reg [6:0]seg3;

    always@(hex_digit)// trocar o parametro por "1", talvez fique melhor. O mesmo para os casos posteriores
    begin
    if (~flag) begin
        case (hex_digit%10)

            4'h0 : seg = 7'b1000000;
            4'h1 : seg = 7'b1111001;
            4'h2 : seg = 7'b0100100;
            4'h3 : seg = 7'b0110000;
            4'h4 : seg = 7'b0011001;
            4'h5 : seg = 7'b0010010;
            4'h6 : seg = 7'b0000010;
            4'h7 : seg = 7'b1111000;
            4'h8 : seg = 7'b0000000;
            4'h9 : seg = 7'b0010000;
        endcase
        case (hex_digit/10)
            4'h0 : seg2 = 7'b1000000;
            4'h1 : seg2 = 7'b1111001;
            4'h2 : seg2 = 7'b0100100;
            4'h3 : seg2 = 7'b0110000;
            4'h4 : seg2 = 7'b0011001;
            4'h5 : seg2 = 7'b0010010;
            4'h6 : seg2 = 7'b0000010;
            4'h7 : seg2 = 7'b1111000;
            4'h8 : seg2 = 7'b0000000;
            4'h9 : seg2 = 7'b0010000;
         endcase
    end else if (flag) begin
        //Falta por o case de blank1, blank2 e blank3, para saver se vai apagar ou nao. Fazer case ou o esquema do ?
        if (blank_3 == 0) begin
            seg = ~7'h00;
        end else begin
            seg = 7'h00;
        end
        if (blank_2 == 0) begin
            seg2 = ~7'h00;
        end else begin
            seg2 = 7'h00;
        end
        if (blank_1 == 0) begin
            seg3 = ~7'h00;
        end else begin
            seg3 = 7'h00;
        end
    end
end
endmodule
//------------------------------------------------------------------------------------------

//-----------------Display 4 ---------------------------------------------------------------
module hex_7seg_operation(hex_digit, seg);
    input [4:0]hex_digit;
    output reg [6:0]seg;

    always@(hex_digit)
    case (hex_digit)

        4'h0 : seg = 7'b1000000;
        4'h1 : seg = 7'b1111001;
        4'h2 : seg = 7'b0100100;
        4'h3 : seg = 7'b0110000;
        4'h4 : seg = 7'b0011001;
        4'h5 : seg = 7'b0010010;
        4'h6 : seg = 7'b0000010;
        4'h7 : seg = 7'b1111000;
        4'h8 : seg = 7'b0000000;
        4'h9 : seg = 7'b0010000;
     endcase

endmodule
//----------------------------------------------------------------------------------------

//------------------Full Adder------------------------------------------------------------
module F_A(a, b, ci, co, s);

    input a, b, ci;
    output reg co, s;

    always @(1)
    begin
        s = ci ^ a ^ b;
        co = ((a & b)) | ci&(a ^ b);
    end

endmodule
//-----------------------------------------------------------------------------

//-----------------Full Subtrator----------------------------------------------
module F_S(a, b, bi, d, bo);

    input a, b, bi;
    output reg d, bo;

    always @(1)
    begin
        d = a ^ b ^ bi;
        bo = (bi & (~(a ^ b))) | ((~a)&b);
    end

endmodule
//------------------------------------------------------------------------------