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  1. /* Automatically generated by nMigen 0.3.dev153+gb86acdc. Do not edit. */
  2. /* Generated by Yosys 0.9+2406 (git sha1 aafaeb66, clang 10.0.0 -fPIC -Os) */
  3.  
  4. (* \nmigen.hierarchy  = "top.top.blink" *)
  5. (* generator = "nMigen" *)
  6. module blink(pixel_rst, pixel_clk, o_led);
  7.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/blink.py:15" *)
  8.   wire [28:0] \$1 ;
  9.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/blink.py:15" *)
  10.   wire [28:0] \$2 ;
  11.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/blink.py:14" *)
  12.   reg [27:0] R_counter = 28'h0000000;
  13.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/blink.py:14" *)
  14.   reg [27:0] \R_counter$next ;
  15.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/blink.py:7" *)
  16.   output [7:0] o_led;
  17.   (* src = "top_vgatest.py:101" *)
  18.   input pixel_clk;
  19.   (* src = "top_vgatest.py:101" *)
  20.   input pixel_rst;
  21.   assign \$2  = R_counter + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/blink.py:15" *) 1'h1;
  22.   always @(posedge pixel_clk)
  23.       R_counter <= \R_counter$next ;
  24.   always @* begin
  25.     \R_counter$next  = \$1 [27:0];
  26.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  27.     casez (pixel_rst)
  28.       1'h1:
  29.           \R_counter$next  = 28'h0000000;
  30.     endcase
  31.   end
  32.   assign \$1  = \$2 ;
  33.   assign o_led = R_counter[27:20];
  34. endmodule
  35.  
  36. (* \nmigen.hierarchy  = "top.top.ecp5pll" *)
  37. (* generator = "nMigen" *)
  38. module ecp5pll(clk25_0__io, pixel_clk, shift_clk, clk);
  39.   (* src = "top_vgatest.py:100" *)
  40.   output clk;
  41.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  42.   input clk25_0__io;
  43.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/ecp5pll.py:26" *)
  44.   wire locked;
  45.   (* src = "top_vgatest.py:101" *)
  46.   output pixel_clk;
  47.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/ecp5pll.py:25" *)
  48.   wire reset;
  49.   (* src = "top_vgatest.py:102" *)
  50.   output shift_clk;
  51.   (* FREQUENCY_PIN_CLKI = "25.0" *)
  52.   (* ICP_CURRENT = "6" *)
  53.   (* LPF_RESISTOR = "16" *)
  54.   (* MFG_ENABLE_FILTEROPAMP = "1" *)
  55.   (* MFG_GMCREF_SEL = "2" *)
  56.   EHXPLLL #(
  57.     .CLKFB_DIV(32'd113),
  58.     .CLKI_DIV(32'd4),
  59.     .CLKOP_CPHASE(32'd28),
  60.     .CLKOP_DIV(32'd28),
  61.     .CLKOP_ENABLE("ENABLED"),
  62.     .CLKOP_FPHASE(32'd0),
  63.     .CLKOS2_CPHASE(32'd2),
  64.     .CLKOS2_DIV(32'd2),
  65.     .CLKOS2_ENABLE("ENABLED"),
  66.     .CLKOS2_FPHASE(32'd0),
  67.     .CLKOS3_DIV(32'd1),
  68.     .CLKOS3_ENABLE("ENABLED"),
  69.     .CLKOS_CPHASE(32'd10),
  70.     .CLKOS_DIV(32'd10),
  71.     .CLKOS_ENABLE("ENABLED"),
  72.     .CLKOS_FPHASE(32'd0),
  73.     .FEEDBK_PATH("INT_OS3")
  74.   ) \U$$0  (
  75.     .CLKI(clk25_0__io),
  76.     .CLKOP(clk),
  77.     .CLKOS(pixel_clk),
  78.     .CLKOS2(shift_clk),
  79.     .LOCK(locked),
  80.     .RST(reset)
  81.   );
  82.   assign reset = 1'h0;
  83. endmodule
  84.  
  85. (* \nmigen.hierarchy  = "top.pin_button_down_0" *)
  86. (* generator = "nMigen" *)
  87. module pin_button_down_0(button_down_0__io, button_down_0__i);
  88.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  89.   output button_down_0__i;
  90.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  91.   input button_down_0__io;
  92.   IB button_down_0_0 (
  93.     .I(button_down_0__io),
  94.     .O(button_down_0__i)
  95.   );
  96. endmodule
  97.  
  98. (* \nmigen.hierarchy  = "top.pin_button_fire_0" *)
  99. (* generator = "nMigen" *)
  100. module pin_button_fire_0(button_fire_0__io, button_fire_0__i);
  101.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  102.   output button_fire_0__i;
  103.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  104.   input button_fire_0__io;
  105.   IB button_fire_0_0 (
  106.     .I(button_fire_0__io),
  107.     .O(button_fire_0__i)
  108.   );
  109. endmodule
  110.  
  111. (* \nmigen.hierarchy  = "top.pin_button_fire_1" *)
  112. (* generator = "nMigen" *)
  113. module pin_button_fire_1(button_fire_1__io, button_fire_1__i);
  114.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  115.   output button_fire_1__i;
  116.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  117.   input button_fire_1__io;
  118.   IB button_fire_1_0 (
  119.     .I(button_fire_1__io),
  120.     .O(button_fire_1__i)
  121.   );
  122. endmodule
  123.  
  124. (* \nmigen.hierarchy  = "top.pin_button_left_0" *)
  125. (* generator = "nMigen" *)
  126. module pin_button_left_0(button_left_0__io, button_left_0__i);
  127.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  128.   output button_left_0__i;
  129.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  130.   input button_left_0__io;
  131.   IB button_left_0_0 (
  132.     .I(button_left_0__io),
  133.     .O(button_left_0__i)
  134.   );
  135. endmodule
  136.  
  137. (* \nmigen.hierarchy  = "top.pin_button_pwr_0" *)
  138. (* generator = "nMigen" *)
  139. module pin_button_pwr_0(button_pwr_0__io, button_pwr_0__i);
  140.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/vendor/lattice_ecp5.py:447" *)
  141.   wire \$1 ;
  142.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  143.   output button_pwr_0__i;
  144.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/vendor/lattice_ecp5.py:446" *)
  145.   wire button_pwr_0__i_n;
  146.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  147.   input button_pwr_0__io;
  148.   assign \$1  = ~ (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/vendor/lattice_ecp5.py:447" *) button_pwr_0__i_n;
  149.   IB button_pwr_0_0 (
  150.     .I(button_pwr_0__io),
  151.     .O(button_pwr_0__i_n)
  152.   );
  153.   assign button_pwr_0__i = \$1 ;
  154. endmodule
  155.  
  156. (* \nmigen.hierarchy  = "top.pin_button_right_0" *)
  157. (* generator = "nMigen" *)
  158. module pin_button_right_0(button_right_0__io, button_right_0__i);
  159.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  160.   output button_right_0__i;
  161.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  162.   input button_right_0__io;
  163.   IB button_right_0_0 (
  164.     .I(button_right_0__io),
  165.     .O(button_right_0__i)
  166.   );
  167. endmodule
  168.  
  169. (* \nmigen.hierarchy  = "top.pin_button_up_0" *)
  170. (* generator = "nMigen" *)
  171. module pin_button_up_0(button_up_0__io, button_up_0__i);
  172.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  173.   output button_up_0__i;
  174.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  175.   input button_up_0__io;
  176.   IB button_up_0_0 (
  177.     .I(button_up_0__io),
  178.     .O(button_up_0__i)
  179.   );
  180. endmodule
  181.  
  182. (* \nmigen.hierarchy  = "top.pin_led_0" *)
  183. (* generator = "nMigen" *)
  184. module pin_led_0(led_0__io, led_0__o);
  185.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  186.   output led_0__io;
  187.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  188.   input led_0__o;
  189.   OB led_0_0 (
  190.     .I(led_0__o),
  191.     .O(led_0__io)
  192.   );
  193. endmodule
  194.  
  195. (* \nmigen.hierarchy  = "top.pin_led_1" *)
  196. (* generator = "nMigen" *)
  197. module pin_led_1(led_1__io, led_1__o);
  198.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  199.   output led_1__io;
  200.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  201.   input led_1__o;
  202.   OB led_1_0 (
  203.     .I(led_1__o),
  204.     .O(led_1__io)
  205.   );
  206. endmodule
  207.  
  208. (* \nmigen.hierarchy  = "top.pin_led_2" *)
  209. (* generator = "nMigen" *)
  210. module pin_led_2(led_2__io, led_2__o);
  211.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  212.   output led_2__io;
  213.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  214.   input led_2__o;
  215.   OB led_2_0 (
  216.     .I(led_2__o),
  217.     .O(led_2__io)
  218.   );
  219. endmodule
  220.  
  221. (* \nmigen.hierarchy  = "top.pin_led_3" *)
  222. (* generator = "nMigen" *)
  223. module pin_led_3(led_3__io, led_3__o);
  224.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  225.   output led_3__io;
  226.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  227.   input led_3__o;
  228.   OB led_3_0 (
  229.     .I(led_3__o),
  230.     .O(led_3__io)
  231.   );
  232. endmodule
  233.  
  234. (* \nmigen.hierarchy  = "top.pin_led_4" *)
  235. (* generator = "nMigen" *)
  236. module pin_led_4(led_4__io, led_4__o);
  237.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  238.   output led_4__io;
  239.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  240.   input led_4__o;
  241.   OB led_4_0 (
  242.     .I(led_4__o),
  243.     .O(led_4__io)
  244.   );
  245. endmodule
  246.  
  247. (* \nmigen.hierarchy  = "top.pin_led_5" *)
  248. (* generator = "nMigen" *)
  249. module pin_led_5(led_5__io, led_5__o);
  250.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  251.   output led_5__io;
  252.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  253.   input led_5__o;
  254.   OB led_5_0 (
  255.     .I(led_5__o),
  256.     .O(led_5__io)
  257.   );
  258. endmodule
  259.  
  260. (* \nmigen.hierarchy  = "top.pin_led_6" *)
  261. (* generator = "nMigen" *)
  262. module pin_led_6(led_6__io, led_6__o);
  263.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  264.   output led_6__io;
  265.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  266.   input led_6__o;
  267.   OB led_6_0 (
  268.     .I(led_6__o),
  269.     .O(led_6__io)
  270.   );
  271. endmodule
  272.  
  273. (* \nmigen.hierarchy  = "top.pin_led_7" *)
  274. (* generator = "nMigen" *)
  275. module pin_led_7(led_7__io, led_7__o);
  276.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  277.   output led_7__io;
  278.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  279.   input led_7__o;
  280.   OB led_7_0 (
  281.     .I(led_7__o),
  282.     .O(led_7__io)
  283.   );
  284. endmodule
  285.  
  286. (* \nmigen.hierarchy  = "top.pin_program_0" *)
  287. (* generator = "nMigen" *)
  288. module pin_program_0(program_0__io);
  289.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/vendor/lattice_ecp5.py:455" *)
  290.   wire \$1 ;
  291.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  292.   output program_0__io;
  293.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  294.   wire program_0__o;
  295.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/vendor/lattice_ecp5.py:454" *)
  296.   wire program_0__o_n;
  297.   assign \$1  = ~ (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/vendor/lattice_ecp5.py:455" *) program_0__o;
  298.   OB program_0_0 (
  299.     .I(program_0__o_n),
  300.     .O(program_0__io)
  301.   );
  302.   assign program_0__o = 1'h0;
  303.   assign program_0__o_n = \$1 ;
  304. endmodule
  305.  
  306. (* \nmigen.hierarchy  = "top" *)
  307. (* top =  1  *)
  308. (* generator = "nMigen" *)
  309. module top(led_1__io, led_2__io, led_3__io, led_4__io, led_5__io, led_6__io, led_7__io, button_pwr_0__io, button_fire_0__io, button_fire_1__io, button_up_0__io, button_down_0__io, button_left_0__io, button_right_0__io, gpdi_0__p, gpdi_1__p, gpdi_2__p, gpdi_3__p, program_0__io, clk25_0__io, led_0__io);
  310.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  311.   input button_down_0__io;
  312.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  313.   input button_fire_0__io;
  314.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  315.   input button_fire_1__io;
  316.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  317.   input button_left_0__io;
  318.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  319.   input button_pwr_0__io;
  320.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  321.   input button_right_0__io;
  322.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  323.   input button_up_0__io;
  324.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  325.   input clk25_0__io;
  326.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:139" *)
  327.   output gpdi_0__p;
  328.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:139" *)
  329.   output gpdi_1__p;
  330.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:139" *)
  331.   output gpdi_2__p;
  332.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:139" *)
  333.   output gpdi_3__p;
  334.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  335.   output led_0__io;
  336.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  337.   output led_1__io;
  338.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  339.   output led_2__io;
  340.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  341.   output led_3__io;
  342.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  343.   output led_4__io;
  344.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  345.   output led_5__io;
  346.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  347.   output led_6__io;
  348.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  349.   output led_7__io;
  350.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  351.   wire pin_button_down_0_button_down_0__i;
  352.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  353.   wire pin_button_fire_0_button_fire_0__i;
  354.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  355.   wire pin_button_fire_1_button_fire_1__i;
  356.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  357.   wire pin_button_left_0_button_left_0__i;
  358.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  359.   wire pin_button_pwr_0_button_pwr_0__i;
  360.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  361.   wire pin_button_right_0_button_right_0__i;
  362.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  363.   wire pin_button_up_0_button_up_0__i;
  364.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  365.   wire pin_led_0_led_0__o;
  366.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  367.   wire pin_led_1_led_1__o;
  368.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  369.   wire pin_led_2_led_2__o;
  370.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  371.   wire pin_led_3_led_3__o;
  372.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  373.   wire pin_led_4_led_4__o;
  374.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  375.   wire pin_led_5_led_5__o;
  376.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  377.   wire pin_led_6_led_6__o;
  378.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:143" *)
  379.   wire pin_led_7_led_7__o;
  380.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  381.   output program_0__io;
  382.   (* src = "top_vgatest.py:60" *)
  383.   wire [6:0] top_i_btn;
  384.   (* src = "top_vgatest.py:62" *)
  385.   wire [3:0] top_o_gpdi_dp;
  386.   (* src = "top_vgatest.py:61" *)
  387.   wire [7:0] top_o_led;
  388.   (* src = "top_vgatest.py:63" *)
  389.   wire top_o_user_programn;
  390.   pin_button_down_0 pin_button_down_0 (
  391.     .button_down_0__i(pin_button_down_0_button_down_0__i),
  392.     .button_down_0__io(button_down_0__io)
  393.   );
  394.   pin_button_fire_0 pin_button_fire_0 (
  395.     .button_fire_0__i(pin_button_fire_0_button_fire_0__i),
  396.     .button_fire_0__io(button_fire_0__io)
  397.   );
  398.   pin_button_fire_1 pin_button_fire_1 (
  399.     .button_fire_1__i(pin_button_fire_1_button_fire_1__i),
  400.     .button_fire_1__io(button_fire_1__io)
  401.   );
  402.   pin_button_left_0 pin_button_left_0 (
  403.     .button_left_0__i(pin_button_left_0_button_left_0__i),
  404.     .button_left_0__io(button_left_0__io)
  405.   );
  406.   pin_button_pwr_0 pin_button_pwr_0 (
  407.     .button_pwr_0__i(pin_button_pwr_0_button_pwr_0__i),
  408.     .button_pwr_0__io(button_pwr_0__io)
  409.   );
  410.   pin_button_right_0 pin_button_right_0 (
  411.     .button_right_0__i(pin_button_right_0_button_right_0__i),
  412.     .button_right_0__io(button_right_0__io)
  413.   );
  414.   pin_button_up_0 pin_button_up_0 (
  415.     .button_up_0__i(pin_button_up_0_button_up_0__i),
  416.     .button_up_0__io(button_up_0__io)
  417.   );
  418.   pin_led_0 pin_led_0 (
  419.     .led_0__io(led_0__io),
  420.     .led_0__o(pin_led_0_led_0__o)
  421.   );
  422.   pin_led_1 pin_led_1 (
  423.     .led_1__io(led_1__io),
  424.     .led_1__o(pin_led_1_led_1__o)
  425.   );
  426.   pin_led_2 pin_led_2 (
  427.     .led_2__io(led_2__io),
  428.     .led_2__o(pin_led_2_led_2__o)
  429.   );
  430.   pin_led_3 pin_led_3 (
  431.     .led_3__io(led_3__io),
  432.     .led_3__o(pin_led_3_led_3__o)
  433.   );
  434.   pin_led_4 pin_led_4 (
  435.     .led_4__io(led_4__io),
  436.     .led_4__o(pin_led_4_led_4__o)
  437.   );
  438.   pin_led_5 pin_led_5 (
  439.     .led_5__io(led_5__io),
  440.     .led_5__o(pin_led_5_led_5__o)
  441.   );
  442.   pin_led_6 pin_led_6 (
  443.     .led_6__io(led_6__io),
  444.     .led_6__o(pin_led_6_led_6__o)
  445.   );
  446.   pin_led_7 pin_led_7 (
  447.     .led_7__io(led_7__io),
  448.     .led_7__o(pin_led_7_led_7__o)
  449.   );
  450.   pin_program_0 pin_program_0 (
  451.     .program_0__io(program_0__io)
  452.   );
  453.   \top$1  top (
  454.     .clk25_0__io(clk25_0__io),
  455.     .i_btn(top_i_btn),
  456.     .o_gpdi_dp(top_o_gpdi_dp),
  457.     .o_led(top_o_led),
  458.     .o_user_programn(top_o_user_programn)
  459.   );
  460.   assign gpdi_3__p = top_o_gpdi_dp[3];
  461.   assign gpdi_2__p = top_o_gpdi_dp[2];
  462.   assign gpdi_1__p = top_o_gpdi_dp[1];
  463.   assign gpdi_0__p = top_o_gpdi_dp[0];
  464.   assign top_i_btn[6] = pin_button_right_0_button_right_0__i;
  465.   assign top_i_btn[5] = pin_button_left_0_button_left_0__i;
  466.   assign top_i_btn[4] = pin_button_down_0_button_down_0__i;
  467.   assign top_i_btn[3] = pin_button_up_0_button_up_0__i;
  468.   assign top_i_btn[2] = pin_button_fire_1_button_fire_1__i;
  469.   assign top_i_btn[1] = pin_button_fire_0_button_fire_0__i;
  470.   assign top_i_btn[0] = pin_button_pwr_0_button_pwr_0__i;
  471.   assign pin_led_7_led_7__o = top_o_led[7];
  472.   assign pin_led_6_led_6__o = top_o_led[6];
  473.   assign pin_led_5_led_5__o = top_o_led[5];
  474.   assign pin_led_4_led_4__o = top_o_user_programn;
  475.   assign pin_led_3_led_3__o = top_o_led[3];
  476.   assign pin_led_2_led_2__o = top_o_led[2];
  477.   assign pin_led_1_led_1__o = top_o_led[1];
  478.   assign pin_led_0_led_0__o = top_o_led[0];
  479. endmodule
  480.  
  481. (* \nmigen.hierarchy  = "top.top" *)
  482. (* generator = "nMigen" *)
  483. module \top$1 (i_btn, o_gpdi_dp, o_user_programn, clk25_0__io, o_led);
  484.   (* src = "top_vgatest.py:97" *)
  485.   wire \$11 ;
  486.   (* src = "top_vgatest.py:97" *)
  487.   wire \$13 ;
  488.   (* src = "top_vgatest.py:95" *)
  489.   wire \$4 ;
  490.   (* src = "top_vgatest.py:96" *)
  491.   wire [20:0] \$6 ;
  492.   (* src = "top_vgatest.py:96" *)
  493.   wire [20:0] \$7 ;
  494.   (* src = "top_vgatest.py:97" *)
  495.   wire \$9 ;
  496.   (* src = "top_vgatest.py:149" *)
  497.   wire [1:0] \$signal ;
  498.   (* src = "top_vgatest.py:149" *)
  499.   wire [1:0] \$signal$1 ;
  500.   (* src = "top_vgatest.py:149" *)
  501.   wire [1:0] \$signal$2 ;
  502.   (* src = "top_vgatest.py:149" *)
  503.   wire [1:0] \$signal$3 ;
  504.   (* src = "top_vgatest.py:94" *)
  505.   reg [19:0] R_delay_reload = 20'h00000;
  506.   (* src = "top_vgatest.py:94" *)
  507.   reg [19:0] \R_delay_reload$next ;
  508.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/blink.py:7" *)
  509.   wire [7:0] blink_o_led;
  510.   (* src = "top_vgatest.py:100" *)
  511.   wire clk;
  512.   (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/build/res.py:129" *)
  513.   input clk25_0__io;
  514.   (* src = "top_vgatest.py:166" *)
  515.   wire [7:0] countblink;
  516.   (* src = "top_vgatest.py:101" *)
  517.   wire ecp5pll_pixel_clk;
  518.   (* src = "top_vgatest.py:102" *)
  519.   wire ecp5pll_shift_clk;
  520.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:33" *)
  521.   wire [7:0] i_b;
  522.   (* src = "top_vgatest.py:60" *)
  523.   input [6:0] i_btn;
  524.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:32" *)
  525.   wire [7:0] i_g;
  526.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:31" *)
  527.   wire [7:0] i_r;
  528.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:30" *)
  529.   wire i_test_picture;
  530.   (* src = "top_vgatest.py:62" *)
  531.   output [3:0] o_gpdi_dp;
  532.   (* src = "top_vgatest.py:61" *)
  533.   output [7:0] o_led;
  534.   (* src = "top_vgatest.py:63" *)
  535.   output o_user_programn;
  536.   (* src = "top_vgatest.py:64" *)
  537.   wire o_wifi_gpio0;
  538.   (* src = "top_vgatest.py:100" *)
  539.   wire rst;
  540.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:17" *)
  541.   wire vga2dvid_i_blank;
  542.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:16" *)
  543.   wire [7:0] vga2dvid_i_blue;
  544.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:15" *)
  545.   wire [7:0] vga2dvid_i_green;
  546.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:18" *)
  547.   wire vga2dvid_i_hsync;
  548.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:14" *)
  549.   wire [7:0] vga2dvid_i_red;
  550.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:19" *)
  551.   wire vga2dvid_i_vsync;
  552.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:27" *)
  553.   wire [1:0] vga2dvid_o_blue;
  554.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:28" *)
  555.   wire [1:0] vga2dvid_o_clk;
  556.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:26" *)
  557.   wire [1:0] vga2dvid_o_green;
  558.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:25" *)
  559.   wire [1:0] vga2dvid_o_red;
  560.   (* src = "top_vgatest.py:117" *)
  561.   wire [7:0] vga_b;
  562.   (* src = "top_vgatest.py:120" *)
  563.   wire vga_blank;
  564.   (* src = "top_vgatest.py:116" *)
  565.   wire [7:0] vga_g;
  566.   (* src = "top_vgatest.py:118" *)
  567.   wire vga_hsync;
  568.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:29" *)
  569.   wire vga_i_clk_en;
  570.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:39" *)
  571.   wire [7:0] vga_o_vga_b;
  572.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:43" *)
  573.   wire vga_o_vga_blank;
  574.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:38" *)
  575.   wire [7:0] vga_o_vga_g;
  576.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:40" *)
  577.   wire vga_o_vga_hsync;
  578.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:37" *)
  579.   wire [7:0] vga_o_vga_r;
  580.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:41" *)
  581.   wire vga_o_vga_vsync;
  582.   (* src = "top_vgatest.py:101" *)
  583.   wire vga_pixel_rst;
  584.   (* src = "top_vgatest.py:115" *)
  585.   wire [7:0] vga_r;
  586.   (* src = "top_vgatest.py:119" *)
  587.   wire vga_vsync;
  588.   assign \$9  = ~ (* src = "top_vgatest.py:97" *) i_btn[0];
  589.   assign \$11  = ~ (* src = "top_vgatest.py:97" *) R_delay_reload[19];
  590.   assign \$13  = \$9  | (* src = "top_vgatest.py:97" *) \$11 ;
  591.   assign \$4  = R_delay_reload[19] == (* src = "top_vgatest.py:95" *) 1'h0;
  592.   assign \$7  = R_delay_reload + (* src = "top_vgatest.py:96" *) 1'h1;
  593.   always @(posedge clk)
  594.       R_delay_reload <= \R_delay_reload$next ;
  595.   blink blink (
  596.     .o_led(blink_o_led),
  597.     .pixel_clk(ecp5pll_pixel_clk),
  598.     .pixel_rst(vga_pixel_rst)
  599.   );
  600.   ODDRX1F ddr0_blue (
  601.     .D0(\$signal$3 [0]),
  602.     .D1(\$signal$3 [1]),
  603.     .Q(o_gpdi_dp[0]),
  604.     .RST(1'h0),
  605.     .SCLK(ecp5pll_shift_clk)
  606.   );
  607.   ODDRX1F ddr0_clock (
  608.     .D0(\$signal [0]),
  609.     .D1(\$signal [1]),
  610.     .Q(o_gpdi_dp[3]),
  611.     .RST(1'h0),
  612.     .SCLK(ecp5pll_shift_clk)
  613.   );
  614.   ODDRX1F ddr0_green (
  615.     .D0(\$signal$2 [0]),
  616.     .D1(\$signal$2 [1]),
  617.     .Q(o_gpdi_dp[1]),
  618.     .RST(1'h0),
  619.     .SCLK(ecp5pll_shift_clk)
  620.   );
  621.   ODDRX1F ddr0_red (
  622.     .D0(\$signal$1 [0]),
  623.     .D1(\$signal$1 [1]),
  624.     .Q(o_gpdi_dp[2]),
  625.     .RST(1'h0),
  626.     .SCLK(ecp5pll_shift_clk)
  627.   );
  628.   ecp5pll ecp5pll (
  629.     .clk(clk),
  630.     .clk25_0__io(clk25_0__io),
  631.     .pixel_clk(ecp5pll_pixel_clk),
  632.     .shift_clk(ecp5pll_shift_clk)
  633.   );
  634.   vga vga (
  635.     .i_clk_en(vga_i_clk_en),
  636.     .o_vga_b(vga_o_vga_b),
  637.     .o_vga_blank(vga_o_vga_blank),
  638.     .o_vga_g(vga_o_vga_g),
  639.     .o_vga_hsync(vga_o_vga_hsync),
  640.     .o_vga_r(vga_o_vga_r),
  641.     .o_vga_vsync(vga_o_vga_vsync),
  642.     .pixel_clk(ecp5pll_pixel_clk),
  643.     .pixel_rst(vga_pixel_rst)
  644.   );
  645.   vga2dvid vga2dvid (
  646.     .i_blank(vga2dvid_i_blank),
  647.     .i_blue(vga2dvid_i_blue),
  648.     .i_green(vga2dvid_i_green),
  649.     .i_hsync(vga2dvid_i_hsync),
  650.     .i_red(vga2dvid_i_red),
  651.     .i_vsync(vga2dvid_i_vsync),
  652.     .o_blue(vga2dvid_o_blue),
  653.     .o_clk(vga2dvid_o_clk),
  654.     .o_green(vga2dvid_o_green),
  655.     .o_red(vga2dvid_o_red),
  656.     .pixel_clk(ecp5pll_pixel_clk),
  657.     .pixel_rst(vga_pixel_rst),
  658.     .shift_clk(ecp5pll_shift_clk)
  659.   );
  660.   always @* begin
  661.     \R_delay_reload$next  = R_delay_reload;
  662.     (* src = "top_vgatest.py:95" *)
  663.     casez (\$4 )
  664.       /* src = "top_vgatest.py:95" */
  665.       1'h1:
  666.           \R_delay_reload$next  = \$6 [19:0];
  667.     endcase
  668.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  669.     casez (rst)
  670.       1'h1:
  671.           \R_delay_reload$next  = 20'h00000;
  672.     endcase
  673.   end
  674.   assign \$6  = \$7 ;
  675.   assign rst = 1'h0;
  676.   assign vga_pixel_rst = 1'h0;
  677.   assign o_led[2] = vga_blank;
  678.   assign o_led[1] = vga_hsync;
  679.   assign o_led[0] = vga_vsync;
  680.   assign o_led[7:6] = countblink[7:6];
  681.   assign o_led[5:3] = 3'h0;
  682.   assign countblink = blink_o_led;
  683.   assign \$signal$3  = vga2dvid_o_blue;
  684.   assign \$signal$2  = vga2dvid_o_green;
  685.   assign \$signal$1  = vga2dvid_o_red;
  686.   assign \$signal  = vga2dvid_o_clk;
  687.   assign vga2dvid_i_blank = vga_blank;
  688.   assign vga2dvid_i_vsync = vga_vsync;
  689.   assign vga2dvid_i_hsync = vga_hsync;
  690.   assign vga2dvid_i_blue = vga_b;
  691.   assign vga2dvid_i_green = vga_g;
  692.   assign vga2dvid_i_red = vga_r;
  693.   assign vga_blank = vga_o_vga_blank;
  694.   assign vga_vsync = vga_o_vga_vsync;
  695.   assign vga_hsync = vga_o_vga_hsync;
  696.   assign vga_b = vga_o_vga_b;
  697.   assign vga_g = vga_o_vga_g;
  698.   assign vga_r = vga_o_vga_r;
  699.   assign i_b = 8'h00;
  700.   assign i_g = 8'h00;
  701.   assign i_r = 8'h00;
  702.   assign i_test_picture = 1'h1;
  703.   assign vga_i_clk_en = 1'h1;
  704.   assign o_user_programn = \$13 ;
  705.   assign o_wifi_gpio0 = i_btn[0];
  706. endmodule
  707.  
  708. (* \nmigen.hierarchy  = "top.top.vga2dvid.u21" *)
  709. (* generator = "nMigen" *)
  710. module u21(pixel_clk, i_data, i_c, i_blank, o_encoded, pixel_rst);
  711.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:25" *)
  712.   wire \$1 ;
  713.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  714.   wire \$101 ;
  715.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  716.   wire \$103 ;
  717.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  718.   wire \$105 ;
  719.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  720.   wire \$107 ;
  721.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  722.   wire \$109 ;
  723.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:30" *)
  724.   wire \$11 ;
  725.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  726.   wire \$111 ;
  727.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  728.   wire \$113 ;
  729.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  730.   wire \$115 ;
  731.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  732.   wire \$117 ;
  733.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  734.   wire \$119 ;
  735.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:97" *)
  736.   wire [9:0] \$121 ;
  737.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  738.   wire \$123 ;
  739.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  740.   wire \$125 ;
  741.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  742.   wire \$127 ;
  743.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  744.   wire \$129 ;
  745.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:31" *)
  746.   wire \$13 ;
  747.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  748.   wire \$131 ;
  749.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  750.   wire \$133 ;
  751.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  752.   wire \$135 ;
  753.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  754.   wire \$137 ;
  755.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  756.   wire \$139 ;
  757.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  758.   wire \$141 ;
  759.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:98" *)
  760.   wire [4:0] \$143 ;
  761.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:98" *)
  762.   wire [4:0] \$144 ;
  763.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:101" *)
  764.   wire [4:0] \$146 ;
  765.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:101" *)
  766.   wire [4:0] \$147 ;
  767.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:105" *)
  768.   wire [5:0] \$149 ;
  769.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:37" *)
  770.   wire \$15 ;
  771.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:105" *)
  772.   wire [4:0] \$150 ;
  773.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:105" *)
  774.   wire [5:0] \$152 ;
  775.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:108" *)
  776.   wire [5:0] \$154 ;
  777.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:108" *)
  778.   wire [4:0] \$155 ;
  779.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:108" *)
  780.   wire [5:0] \$157 ;
  781.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:37" *)
  782.   wire \$16 ;
  783.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:38" *)
  784.   wire \$19 ;
  785.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:38" *)
  786.   wire \$20 ;
  787.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:39" *)
  788.   wire \$23 ;
  789.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:39" *)
  790.   wire \$24 ;
  791.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:40" *)
  792.   wire \$27 ;
  793.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:40" *)
  794.   wire \$28 ;
  795.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:26" *)
  796.   wire \$3 ;
  797.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:41" *)
  798.   wire \$31 ;
  799.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:41" *)
  800.   wire \$32 ;
  801.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:42" *)
  802.   wire \$35 ;
  803.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:42" *)
  804.   wire \$36 ;
  805.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:43" *)
  806.   wire \$39 ;
  807.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:43" *)
  808.   wire \$40 ;
  809.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  810.   wire [8:0] \$43 ;
  811.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  812.   wire [1:0] \$44 ;
  813.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  814.   wire [2:0] \$46 ;
  815.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  816.   wire [3:0] \$48 ;
  817.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:27" *)
  818.   wire \$5 ;
  819.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  820.   wire [4:0] \$50 ;
  821.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  822.   wire [5:0] \$52 ;
  823.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  824.   wire [6:0] \$54 ;
  825.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  826.   wire [7:0] \$56 ;
  827.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  828.   wire [8:0] \$58 ;
  829.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  830.   wire \$60 ;
  831.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  832.   wire \$62 ;
  833.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  834.   wire \$64 ;
  835.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  836.   wire \$66 ;
  837.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  838.   wire \$68 ;
  839.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:28" *)
  840.   wire \$7 ;
  841.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  842.   wire \$70 ;
  843.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  844.   wire \$72 ;
  845.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  846.   wire \$74 ;
  847.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  848.   wire \$76 ;
  849.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  850.   wire \$78 ;
  851.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:63" *)
  852.   wire [8:0] \$80 ;
  853.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:66" *)
  854.   wire [8:0] \$82 ;
  855.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  856.   wire [11:0] \$84 ;
  857.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  858.   wire [4:0] \$85 ;
  859.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  860.   wire [5:0] \$87 ;
  861.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  862.   wire [6:0] \$89 ;
  863.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:29" *)
  864.   wire \$9 ;
  865.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  866.   wire [7:0] \$91 ;
  867.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  868.   wire [8:0] \$93 ;
  869.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  870.   wire [9:0] \$95 ;
  871.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  872.   wire [10:0] \$97 ;
  873.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  874.   wire [11:0] \$99 ;
  875.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:18" *)
  876.   reg [8:0] data_word;
  877.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:20" *)
  878.   wire [3:0] data_word_disparity;
  879.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:19" *)
  880.   reg [8:0] data_word_inv;
  881.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:21" *)
  882.   reg [3:0] dc_bias = 4'h0;
  883.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:21" *)
  884.   reg [3:0] \dc_bias$next ;
  885.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:9" *)
  886.   input i_blank;
  887.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:8" *)
  888.   input [1:0] i_c;
  889.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:7" *)
  890.   input [7:0] i_data;
  891.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:10" *)
  892.   output [9:0] o_encoded;
  893.   reg [9:0] o_encoded = 10'h000;
  894.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:10" *)
  895.   reg [9:0] \o_encoded$next ;
  896.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:17" *)
  897.   wire [3:0] ones;
  898.   (* src = "top_vgatest.py:101" *)
  899.   input pixel_clk;
  900.   (* src = "top_vgatest.py:101" *)
  901.   input pixel_rst;
  902.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:16" *)
  903.   wire [8:0] xnored;
  904.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:15" *)
  905.   wire [8:0] xored;
  906.   assign \$9  = i_data[5] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:29" *) xored[4];
  907.   assign \$99  = \$97  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[7];
  908.   assign \$101  = dc_bias == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) 1'h0;
  909.   assign \$103  = data_word_disparity == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) 1'h0;
  910.   assign \$105  = \$101  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) \$103 ;
  911.   assign \$107  = dc_bias[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) 1'h0;
  912.   assign \$109  = data_word_disparity[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) 1'h0;
  913.   assign \$111  = \$107  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) \$109 ;
  914.   assign \$113  = dc_bias[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) 1'h1;
  915.   assign \$115  = data_word_disparity[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) 1'h1;
  916.   assign \$117  = \$113  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) \$115 ;
  917.   assign \$11  = i_data[6] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:30" *) xored[5];
  918.   assign \$119  = \$111  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) \$117 ;
  919.   assign \$121  = + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:97" *) { 1'h1, data_word[7:0] };
  920.   assign \$123  = dc_bias == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) 1'h0;
  921.   assign \$125  = data_word_disparity == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) 1'h0;
  922.   assign \$127  = \$123  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) \$125 ;
  923.   assign \$129  = dc_bias[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) 1'h0;
  924.   assign \$131  = data_word_disparity[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) 1'h0;
  925.   assign \$133  = \$129  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) \$131 ;
  926.   assign \$135  = dc_bias[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) 1'h1;
  927.   assign \$137  = data_word_disparity[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) 1'h1;
  928.   assign \$13  = i_data[7] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:31" *) xored[6];
  929.   assign \$139  = \$135  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) \$137 ;
  930.   assign \$141  = \$133  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) \$139 ;
  931.   assign \$144  = dc_bias + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:98" *) data_word_disparity;
  932.   assign \$147  = dc_bias - (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:101" *) data_word_disparity;
  933.   assign \$150  = dc_bias + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:105" *) data_word[8];
  934.   assign \$152  = \$150  - (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:105" *) data_word_disparity;
  935.   assign \$155  = dc_bias - (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:108" *) data_word_inv[8];
  936.   assign \$157  = \$155  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:108" *) data_word_disparity;
  937.   assign \$16  = i_data[1] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:37" *) xnored[0];
  938.   assign \$15  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:37" *) \$16 ;
  939.   assign \$1  = i_data[1] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:25" *) xored[0];
  940.   assign \$20  = i_data[2] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:38" *) xnored[1];
  941.   assign \$19  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:38" *) \$20 ;
  942.   assign \$24  = i_data[3] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:39" *) xnored[2];
  943.   assign \$23  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:39" *) \$24 ;
  944.   assign \$28  = i_data[4] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:40" *) xnored[3];
  945.   assign \$27  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:40" *) \$28 ;
  946.   assign \$32  = i_data[5] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:41" *) xnored[4];
  947.   assign \$31  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:41" *) \$32 ;
  948.   assign \$36  = i_data[6] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:42" *) xnored[5];
  949.   assign \$35  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:42" *) \$36 ;
  950.   assign \$3  = i_data[2] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:26" *) xored[1];
  951.   assign \$40  = i_data[7] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:43" *) xnored[6];
  952.   assign \$39  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:43" *) \$40 ;
  953.   assign \$44  = 1'h0 + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[0];
  954.   assign \$46  = \$44  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[1];
  955.   assign \$48  = \$46  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[2];
  956.   assign \$50  = \$48  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[3];
  957.   assign \$52  = \$50  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[4];
  958.   assign \$54  = \$52  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[5];
  959.   assign \$56  = \$54  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[6];
  960.   assign \$58  = \$56  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[7];
  961.   assign \$5  = i_data[3] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:27" *) xored[2];
  962.   assign \$60  = ones > (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 3'h4;
  963.   assign \$62  = ones == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 3'h4;
  964.   assign \$64  = i_data[0] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 1'h0;
  965.   assign \$66  = \$62  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) \$64 ;
  966.   assign \$68  = \$60  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) \$66 ;
  967.   assign \$70  = ones > (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 3'h4;
  968.   assign \$72  = ones == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 3'h4;
  969.   assign \$74  = i_data[0] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 1'h0;
  970.   assign \$76  = \$72  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) \$74 ;
  971.   assign \$78  = \$70  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) \$76 ;
  972.   assign \$7  = i_data[4] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:28" *) xored[3];
  973.   assign \$80  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:63" *) xnored;
  974.   assign \$82  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:66" *) xored;
  975.   assign \$85  = 4'hc + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[0];
  976.   assign \$87  = \$85  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[1];
  977.   assign \$89  = \$87  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[2];
  978.   assign \$91  = \$89  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[3];
  979.   assign \$93  = \$91  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[4];
  980.   assign \$95  = \$93  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[5];
  981.   assign \$97  = \$95  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[6];
  982.   always @(posedge pixel_clk)
  983.       dc_bias <= \dc_bias$next ;
  984.   always @(posedge pixel_clk)
  985.       o_encoded <= \o_encoded$next ;
  986.   always @* begin
  987.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  988.     casez (\$68 )
  989.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" */
  990.       1'h1:
  991.           data_word = xnored;
  992.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:64" */
  993.       default:
  994.           data_word = xored;
  995.     endcase
  996.   end
  997.   always @* begin
  998.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  999.     casez (\$78 )
  1000.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" */
  1001.       1'h1:
  1002.           data_word_inv = \$80 ;
  1003.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:64" */
  1004.       default:
  1005.           data_word_inv = \$82 ;
  1006.     endcase
  1007.   end
  1008.   always @* begin
  1009.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:82" *)
  1010.     casez (i_blank)
  1011.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:82" */
  1012.       1'h1:
  1013.           (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:83" *)
  1014.           casez (i_c)
  1015.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:84" */
  1016.             2'h0:
  1017.                 \o_encoded$next  = 10'h354;
  1018.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:86" */
  1019.             2'h1:
  1020.                 \o_encoded$next  = 10'h0ab;
  1021.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:88" */
  1022.             2'h2:
  1023.                 \o_encoded$next  = 10'h154;
  1024.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:90" */
  1025.             default:
  1026.                 \o_encoded$next  = 10'h2ab;
  1027.           endcase
  1028.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:93" */
  1029.       default:
  1030.           (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1031.           casez ({ \$119 , \$105  })
  1032.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" */
  1033.             2'b?1:
  1034.                 (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:96" *)
  1035.                 casez (data_word[8])
  1036.                   /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:96" */
  1037.                   1'h1:
  1038.                       \o_encoded$next  = \$121 ;
  1039.                   /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:99" */
  1040.                   default:
  1041.                       \o_encoded$next  = { 2'h2, data_word_inv[7:0] };
  1042.                 endcase
  1043.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" */
  1044.             2'b1?:
  1045.                 \o_encoded$next  = { 1'h1, data_word[8], data_word_inv[7:0] };
  1046.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:106" */
  1047.             default:
  1048.                 \o_encoded$next  = { 1'h0, data_word };
  1049.           endcase
  1050.     endcase
  1051.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  1052.     casez (pixel_rst)
  1053.       1'h1:
  1054.           \o_encoded$next  = 10'h000;
  1055.     endcase
  1056.   end
  1057.   always @* begin
  1058.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:82" *)
  1059.     casez (i_blank)
  1060.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:82" */
  1061.       1'h1:
  1062.           \dc_bias$next  = 4'h0;
  1063.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:93" */
  1064.       default:
  1065.           (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1066.           casez ({ \$141 , \$127  })
  1067.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" */
  1068.             2'b?1:
  1069.                 (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:96" *)
  1070.                 casez (data_word[8])
  1071.                   /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:96" */
  1072.                   1'h1:
  1073.                       \dc_bias$next  = \$143 [3:0];
  1074.                   /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:99" */
  1075.                   default:
  1076.                       \dc_bias$next  = \$146 [3:0];
  1077.                 endcase
  1078.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" */
  1079.             2'b1?:
  1080.                 \dc_bias$next  = \$149 [3:0];
  1081.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:106" */
  1082.             default:
  1083.                 \dc_bias$next  = \$154 [3:0];
  1084.           endcase
  1085.     endcase
  1086.   end
  1087.   assign \$43  = \$58 ;
  1088.   assign \$84  = \$99 ;
  1089.   assign \$143  = \$144 ;
  1090.   assign \$146  = \$147 ;
  1091.   assign \$149  = \$152 ;
  1092.   assign \$154  = \$157 ;
  1093.   assign data_word_disparity = \$99 [3:0];
  1094.   assign ones = \$58 [3:0];
  1095.   assign xnored[8] = 1'h0;
  1096.   assign xnored[7] = \$39 ;
  1097.   assign xnored[6] = \$35 ;
  1098.   assign xnored[5] = \$31 ;
  1099.   assign xnored[4] = \$27 ;
  1100.   assign xnored[3] = \$23 ;
  1101.   assign xnored[2] = \$19 ;
  1102.   assign xnored[1] = \$15 ;
  1103.   assign xnored[0] = i_data[0];
  1104.   assign xored[8] = 1'h1;
  1105.   assign xored[7] = \$13 ;
  1106.   assign xored[6] = \$11 ;
  1107.   assign xored[5] = \$9 ;
  1108.   assign xored[4] = \$7 ;
  1109.   assign xored[3] = \$5 ;
  1110.   assign xored[2] = \$3 ;
  1111.   assign xored[1] = \$1 ;
  1112.   assign xored[0] = i_data[0];
  1113. endmodule
  1114.  
  1115. (* \nmigen.hierarchy  = "top.top.vga2dvid.u22" *)
  1116. (* generator = "nMigen" *)
  1117. module u22(pixel_clk, i_data, i_c, i_blank, o_encoded, pixel_rst);
  1118.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:25" *)
  1119.   wire \$1 ;
  1120.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1121.   wire \$101 ;
  1122.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1123.   wire \$103 ;
  1124.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1125.   wire \$105 ;
  1126.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  1127.   wire \$107 ;
  1128.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  1129.   wire \$109 ;
  1130.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:30" *)
  1131.   wire \$11 ;
  1132.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  1133.   wire \$111 ;
  1134.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  1135.   wire \$113 ;
  1136.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  1137.   wire \$115 ;
  1138.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  1139.   wire \$117 ;
  1140.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  1141.   wire \$119 ;
  1142.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:97" *)
  1143.   wire [9:0] \$121 ;
  1144.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1145.   wire \$123 ;
  1146.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1147.   wire \$125 ;
  1148.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1149.   wire \$127 ;
  1150.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  1151.   wire \$129 ;
  1152.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:31" *)
  1153.   wire \$13 ;
  1154.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  1155.   wire \$131 ;
  1156.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  1157.   wire \$133 ;
  1158.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  1159.   wire \$135 ;
  1160.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  1161.   wire \$137 ;
  1162.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  1163.   wire \$139 ;
  1164.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  1165.   wire \$141 ;
  1166.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:98" *)
  1167.   wire [4:0] \$143 ;
  1168.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:98" *)
  1169.   wire [4:0] \$144 ;
  1170.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:101" *)
  1171.   wire [4:0] \$146 ;
  1172.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:101" *)
  1173.   wire [4:0] \$147 ;
  1174.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:105" *)
  1175.   wire [5:0] \$149 ;
  1176.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:37" *)
  1177.   wire \$15 ;
  1178.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:105" *)
  1179.   wire [4:0] \$150 ;
  1180.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:105" *)
  1181.   wire [5:0] \$152 ;
  1182.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:108" *)
  1183.   wire [5:0] \$154 ;
  1184.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:108" *)
  1185.   wire [4:0] \$155 ;
  1186.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:108" *)
  1187.   wire [5:0] \$157 ;
  1188.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:37" *)
  1189.   wire \$16 ;
  1190.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:38" *)
  1191.   wire \$19 ;
  1192.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:38" *)
  1193.   wire \$20 ;
  1194.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:39" *)
  1195.   wire \$23 ;
  1196.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:39" *)
  1197.   wire \$24 ;
  1198.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:40" *)
  1199.   wire \$27 ;
  1200.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:40" *)
  1201.   wire \$28 ;
  1202.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:26" *)
  1203.   wire \$3 ;
  1204.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:41" *)
  1205.   wire \$31 ;
  1206.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:41" *)
  1207.   wire \$32 ;
  1208.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:42" *)
  1209.   wire \$35 ;
  1210.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:42" *)
  1211.   wire \$36 ;
  1212.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:43" *)
  1213.   wire \$39 ;
  1214.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:43" *)
  1215.   wire \$40 ;
  1216.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1217.   wire [8:0] \$43 ;
  1218.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1219.   wire [1:0] \$44 ;
  1220.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1221.   wire [2:0] \$46 ;
  1222.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1223.   wire [3:0] \$48 ;
  1224.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:27" *)
  1225.   wire \$5 ;
  1226.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1227.   wire [4:0] \$50 ;
  1228.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1229.   wire [5:0] \$52 ;
  1230.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1231.   wire [6:0] \$54 ;
  1232.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1233.   wire [7:0] \$56 ;
  1234.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1235.   wire [8:0] \$58 ;
  1236.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1237.   wire \$60 ;
  1238.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1239.   wire \$62 ;
  1240.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1241.   wire \$64 ;
  1242.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1243.   wire \$66 ;
  1244.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1245.   wire \$68 ;
  1246.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:28" *)
  1247.   wire \$7 ;
  1248.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1249.   wire \$70 ;
  1250.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1251.   wire \$72 ;
  1252.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1253.   wire \$74 ;
  1254.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1255.   wire \$76 ;
  1256.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1257.   wire \$78 ;
  1258.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:63" *)
  1259.   wire [8:0] \$80 ;
  1260.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:66" *)
  1261.   wire [8:0] \$82 ;
  1262.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1263.   wire [11:0] \$84 ;
  1264.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1265.   wire [4:0] \$85 ;
  1266.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1267.   wire [5:0] \$87 ;
  1268.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1269.   wire [6:0] \$89 ;
  1270.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:29" *)
  1271.   wire \$9 ;
  1272.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1273.   wire [7:0] \$91 ;
  1274.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1275.   wire [8:0] \$93 ;
  1276.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1277.   wire [9:0] \$95 ;
  1278.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1279.   wire [10:0] \$97 ;
  1280.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1281.   wire [11:0] \$99 ;
  1282.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:18" *)
  1283.   reg [8:0] data_word;
  1284.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:20" *)
  1285.   wire [3:0] data_word_disparity;
  1286.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:19" *)
  1287.   reg [8:0] data_word_inv;
  1288.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:21" *)
  1289.   reg [3:0] dc_bias = 4'h0;
  1290.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:21" *)
  1291.   reg [3:0] \dc_bias$next ;
  1292.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:9" *)
  1293.   input i_blank;
  1294.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:8" *)
  1295.   input [1:0] i_c;
  1296.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:7" *)
  1297.   input [7:0] i_data;
  1298.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:10" *)
  1299.   output [9:0] o_encoded;
  1300.   reg [9:0] o_encoded = 10'h000;
  1301.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:10" *)
  1302.   reg [9:0] \o_encoded$next ;
  1303.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:17" *)
  1304.   wire [3:0] ones;
  1305.   (* src = "top_vgatest.py:101" *)
  1306.   input pixel_clk;
  1307.   (* src = "top_vgatest.py:101" *)
  1308.   input pixel_rst;
  1309.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:16" *)
  1310.   wire [8:0] xnored;
  1311.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:15" *)
  1312.   wire [8:0] xored;
  1313.   assign \$9  = i_data[5] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:29" *) xored[4];
  1314.   assign \$99  = \$97  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[7];
  1315.   assign \$101  = dc_bias == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) 1'h0;
  1316.   assign \$103  = data_word_disparity == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) 1'h0;
  1317.   assign \$105  = \$101  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) \$103 ;
  1318.   assign \$107  = dc_bias[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) 1'h0;
  1319.   assign \$109  = data_word_disparity[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) 1'h0;
  1320.   assign \$111  = \$107  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) \$109 ;
  1321.   assign \$113  = dc_bias[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) 1'h1;
  1322.   assign \$115  = data_word_disparity[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) 1'h1;
  1323.   assign \$117  = \$113  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) \$115 ;
  1324.   assign \$11  = i_data[6] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:30" *) xored[5];
  1325.   assign \$119  = \$111  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) \$117 ;
  1326.   assign \$121  = + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:97" *) { 1'h1, data_word[7:0] };
  1327.   assign \$123  = dc_bias == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) 1'h0;
  1328.   assign \$125  = data_word_disparity == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) 1'h0;
  1329.   assign \$127  = \$123  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) \$125 ;
  1330.   assign \$129  = dc_bias[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) 1'h0;
  1331.   assign \$131  = data_word_disparity[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) 1'h0;
  1332.   assign \$133  = \$129  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) \$131 ;
  1333.   assign \$135  = dc_bias[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) 1'h1;
  1334.   assign \$137  = data_word_disparity[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) 1'h1;
  1335.   assign \$13  = i_data[7] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:31" *) xored[6];
  1336.   assign \$139  = \$135  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) \$137 ;
  1337.   assign \$141  = \$133  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) \$139 ;
  1338.   assign \$144  = dc_bias + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:98" *) data_word_disparity;
  1339.   assign \$147  = dc_bias - (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:101" *) data_word_disparity;
  1340.   assign \$150  = dc_bias + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:105" *) data_word[8];
  1341.   assign \$152  = \$150  - (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:105" *) data_word_disparity;
  1342.   assign \$155  = dc_bias - (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:108" *) data_word_inv[8];
  1343.   assign \$157  = \$155  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:108" *) data_word_disparity;
  1344.   assign \$16  = i_data[1] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:37" *) xnored[0];
  1345.   assign \$15  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:37" *) \$16 ;
  1346.   assign \$1  = i_data[1] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:25" *) xored[0];
  1347.   assign \$20  = i_data[2] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:38" *) xnored[1];
  1348.   assign \$19  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:38" *) \$20 ;
  1349.   assign \$24  = i_data[3] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:39" *) xnored[2];
  1350.   assign \$23  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:39" *) \$24 ;
  1351.   assign \$28  = i_data[4] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:40" *) xnored[3];
  1352.   assign \$27  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:40" *) \$28 ;
  1353.   assign \$32  = i_data[5] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:41" *) xnored[4];
  1354.   assign \$31  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:41" *) \$32 ;
  1355.   assign \$36  = i_data[6] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:42" *) xnored[5];
  1356.   assign \$35  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:42" *) \$36 ;
  1357.   assign \$3  = i_data[2] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:26" *) xored[1];
  1358.   assign \$40  = i_data[7] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:43" *) xnored[6];
  1359.   assign \$39  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:43" *) \$40 ;
  1360.   assign \$44  = 1'h0 + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[0];
  1361.   assign \$46  = \$44  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[1];
  1362.   assign \$48  = \$46  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[2];
  1363.   assign \$50  = \$48  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[3];
  1364.   assign \$52  = \$50  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[4];
  1365.   assign \$54  = \$52  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[5];
  1366.   assign \$56  = \$54  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[6];
  1367.   assign \$58  = \$56  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[7];
  1368.   assign \$5  = i_data[3] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:27" *) xored[2];
  1369.   assign \$60  = ones > (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 3'h4;
  1370.   assign \$62  = ones == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 3'h4;
  1371.   assign \$64  = i_data[0] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 1'h0;
  1372.   assign \$66  = \$62  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) \$64 ;
  1373.   assign \$68  = \$60  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) \$66 ;
  1374.   assign \$70  = ones > (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 3'h4;
  1375.   assign \$72  = ones == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 3'h4;
  1376.   assign \$74  = i_data[0] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 1'h0;
  1377.   assign \$76  = \$72  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) \$74 ;
  1378.   assign \$78  = \$70  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) \$76 ;
  1379.   assign \$7  = i_data[4] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:28" *) xored[3];
  1380.   assign \$80  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:63" *) xnored;
  1381.   assign \$82  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:66" *) xored;
  1382.   assign \$85  = 4'hc + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[0];
  1383.   assign \$87  = \$85  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[1];
  1384.   assign \$89  = \$87  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[2];
  1385.   assign \$91  = \$89  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[3];
  1386.   assign \$93  = \$91  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[4];
  1387.   assign \$95  = \$93  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[5];
  1388.   assign \$97  = \$95  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[6];
  1389.   always @(posedge pixel_clk)
  1390.       dc_bias <= \dc_bias$next ;
  1391.   always @(posedge pixel_clk)
  1392.       o_encoded <= \o_encoded$next ;
  1393.   always @* begin
  1394.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1395.     casez (\$68 )
  1396.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" */
  1397.       1'h1:
  1398.           data_word = xnored;
  1399.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:64" */
  1400.       default:
  1401.           data_word = xored;
  1402.     endcase
  1403.   end
  1404.   always @* begin
  1405.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1406.     casez (\$78 )
  1407.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" */
  1408.       1'h1:
  1409.           data_word_inv = \$80 ;
  1410.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:64" */
  1411.       default:
  1412.           data_word_inv = \$82 ;
  1413.     endcase
  1414.   end
  1415.   always @* begin
  1416.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:82" *)
  1417.     casez (i_blank)
  1418.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:82" */
  1419.       1'h1:
  1420.           (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:83" *)
  1421.           casez (i_c)
  1422.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:84" */
  1423.             2'h0:
  1424.                 \o_encoded$next  = 10'h354;
  1425.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:86" */
  1426.             2'h1:
  1427.                 \o_encoded$next  = 10'h0ab;
  1428.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:88" */
  1429.             2'h2:
  1430.                 \o_encoded$next  = 10'h154;
  1431.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:90" */
  1432.             default:
  1433.                 \o_encoded$next  = 10'h2ab;
  1434.           endcase
  1435.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:93" */
  1436.       default:
  1437.           (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1438.           casez ({ \$119 , \$105  })
  1439.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" */
  1440.             2'b?1:
  1441.                 (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:96" *)
  1442.                 casez (data_word[8])
  1443.                   /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:96" */
  1444.                   1'h1:
  1445.                       \o_encoded$next  = \$121 ;
  1446.                   /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:99" */
  1447.                   default:
  1448.                       \o_encoded$next  = { 2'h2, data_word_inv[7:0] };
  1449.                 endcase
  1450.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" */
  1451.             2'b1?:
  1452.                 \o_encoded$next  = { 1'h1, data_word[8], data_word_inv[7:0] };
  1453.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:106" */
  1454.             default:
  1455.                 \o_encoded$next  = { 1'h0, data_word };
  1456.           endcase
  1457.     endcase
  1458.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  1459.     casez (pixel_rst)
  1460.       1'h1:
  1461.           \o_encoded$next  = 10'h000;
  1462.     endcase
  1463.   end
  1464.   always @* begin
  1465.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:82" *)
  1466.     casez (i_blank)
  1467.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:82" */
  1468.       1'h1:
  1469.           \dc_bias$next  = 4'h0;
  1470.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:93" */
  1471.       default:
  1472.           (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1473.           casez ({ \$141 , \$127  })
  1474.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" */
  1475.             2'b?1:
  1476.                 (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:96" *)
  1477.                 casez (data_word[8])
  1478.                   /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:96" */
  1479.                   1'h1:
  1480.                       \dc_bias$next  = \$143 [3:0];
  1481.                   /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:99" */
  1482.                   default:
  1483.                       \dc_bias$next  = \$146 [3:0];
  1484.                 endcase
  1485.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" */
  1486.             2'b1?:
  1487.                 \dc_bias$next  = \$149 [3:0];
  1488.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:106" */
  1489.             default:
  1490.                 \dc_bias$next  = \$154 [3:0];
  1491.           endcase
  1492.     endcase
  1493.   end
  1494.   assign \$43  = \$58 ;
  1495.   assign \$84  = \$99 ;
  1496.   assign \$143  = \$144 ;
  1497.   assign \$146  = \$147 ;
  1498.   assign \$149  = \$152 ;
  1499.   assign \$154  = \$157 ;
  1500.   assign data_word_disparity = \$99 [3:0];
  1501.   assign ones = \$58 [3:0];
  1502.   assign xnored[8] = 1'h0;
  1503.   assign xnored[7] = \$39 ;
  1504.   assign xnored[6] = \$35 ;
  1505.   assign xnored[5] = \$31 ;
  1506.   assign xnored[4] = \$27 ;
  1507.   assign xnored[3] = \$23 ;
  1508.   assign xnored[2] = \$19 ;
  1509.   assign xnored[1] = \$15 ;
  1510.   assign xnored[0] = i_data[0];
  1511.   assign xored[8] = 1'h1;
  1512.   assign xored[7] = \$13 ;
  1513.   assign xored[6] = \$11 ;
  1514.   assign xored[5] = \$9 ;
  1515.   assign xored[4] = \$7 ;
  1516.   assign xored[3] = \$5 ;
  1517.   assign xored[2] = \$3 ;
  1518.   assign xored[1] = \$1 ;
  1519.   assign xored[0] = i_data[0];
  1520. endmodule
  1521.  
  1522. (* \nmigen.hierarchy  = "top.top.vga2dvid.u23" *)
  1523. (* generator = "nMigen" *)
  1524. module u23(pixel_clk, i_data, i_c, i_blank, o_encoded, pixel_rst);
  1525.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:25" *)
  1526.   wire \$1 ;
  1527.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1528.   wire \$101 ;
  1529.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1530.   wire \$103 ;
  1531.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1532.   wire \$105 ;
  1533.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  1534.   wire \$107 ;
  1535.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  1536.   wire \$109 ;
  1537.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:30" *)
  1538.   wire \$11 ;
  1539.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  1540.   wire \$111 ;
  1541.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  1542.   wire \$113 ;
  1543.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  1544.   wire \$115 ;
  1545.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  1546.   wire \$117 ;
  1547.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  1548.   wire \$119 ;
  1549.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:97" *)
  1550.   wire [9:0] \$121 ;
  1551.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1552.   wire \$123 ;
  1553.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1554.   wire \$125 ;
  1555.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1556.   wire \$127 ;
  1557.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  1558.   wire \$129 ;
  1559.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:31" *)
  1560.   wire \$13 ;
  1561.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  1562.   wire \$131 ;
  1563.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  1564.   wire \$133 ;
  1565.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  1566.   wire \$135 ;
  1567.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  1568.   wire \$137 ;
  1569.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *)
  1570.   wire \$139 ;
  1571.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *)
  1572.   wire \$141 ;
  1573.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:98" *)
  1574.   wire [4:0] \$143 ;
  1575.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:98" *)
  1576.   wire [4:0] \$144 ;
  1577.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:101" *)
  1578.   wire [4:0] \$146 ;
  1579.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:101" *)
  1580.   wire [4:0] \$147 ;
  1581.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:105" *)
  1582.   wire [5:0] \$149 ;
  1583.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:37" *)
  1584.   wire \$15 ;
  1585.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:105" *)
  1586.   wire [4:0] \$150 ;
  1587.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:105" *)
  1588.   wire [5:0] \$152 ;
  1589.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:108" *)
  1590.   wire [5:0] \$154 ;
  1591.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:108" *)
  1592.   wire [4:0] \$155 ;
  1593.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:108" *)
  1594.   wire [5:0] \$157 ;
  1595.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:37" *)
  1596.   wire \$16 ;
  1597.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:38" *)
  1598.   wire \$19 ;
  1599.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:38" *)
  1600.   wire \$20 ;
  1601.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:39" *)
  1602.   wire \$23 ;
  1603.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:39" *)
  1604.   wire \$24 ;
  1605.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:40" *)
  1606.   wire \$27 ;
  1607.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:40" *)
  1608.   wire \$28 ;
  1609.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:26" *)
  1610.   wire \$3 ;
  1611.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:41" *)
  1612.   wire \$31 ;
  1613.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:41" *)
  1614.   wire \$32 ;
  1615.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:42" *)
  1616.   wire \$35 ;
  1617.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:42" *)
  1618.   wire \$36 ;
  1619.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:43" *)
  1620.   wire \$39 ;
  1621.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:43" *)
  1622.   wire \$40 ;
  1623.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1624.   wire [8:0] \$43 ;
  1625.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1626.   wire [1:0] \$44 ;
  1627.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1628.   wire [2:0] \$46 ;
  1629.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1630.   wire [3:0] \$48 ;
  1631.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:27" *)
  1632.   wire \$5 ;
  1633.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1634.   wire [4:0] \$50 ;
  1635.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1636.   wire [5:0] \$52 ;
  1637.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1638.   wire [6:0] \$54 ;
  1639.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1640.   wire [7:0] \$56 ;
  1641.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *)
  1642.   wire [8:0] \$58 ;
  1643.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1644.   wire \$60 ;
  1645.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1646.   wire \$62 ;
  1647.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1648.   wire \$64 ;
  1649.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1650.   wire \$66 ;
  1651.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1652.   wire \$68 ;
  1653.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:28" *)
  1654.   wire \$7 ;
  1655.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1656.   wire \$70 ;
  1657.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1658.   wire \$72 ;
  1659.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1660.   wire \$74 ;
  1661.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1662.   wire \$76 ;
  1663.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1664.   wire \$78 ;
  1665.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:63" *)
  1666.   wire [8:0] \$80 ;
  1667.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:66" *)
  1668.   wire [8:0] \$82 ;
  1669.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1670.   wire [11:0] \$84 ;
  1671.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1672.   wire [4:0] \$85 ;
  1673.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1674.   wire [5:0] \$87 ;
  1675.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1676.   wire [6:0] \$89 ;
  1677.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:29" *)
  1678.   wire \$9 ;
  1679.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1680.   wire [7:0] \$91 ;
  1681.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1682.   wire [8:0] \$93 ;
  1683.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1684.   wire [9:0] \$95 ;
  1685.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1686.   wire [10:0] \$97 ;
  1687.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *)
  1688.   wire [11:0] \$99 ;
  1689.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:18" *)
  1690.   reg [8:0] data_word;
  1691.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:20" *)
  1692.   wire [3:0] data_word_disparity;
  1693.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:19" *)
  1694.   reg [8:0] data_word_inv;
  1695.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:21" *)
  1696.   reg [3:0] dc_bias = 4'h0;
  1697.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:21" *)
  1698.   reg [3:0] \dc_bias$next ;
  1699.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:9" *)
  1700.   input i_blank;
  1701.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:8" *)
  1702.   input [1:0] i_c;
  1703.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:7" *)
  1704.   input [7:0] i_data;
  1705.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:10" *)
  1706.   output [9:0] o_encoded;
  1707.   reg [9:0] o_encoded = 10'h000;
  1708.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:10" *)
  1709.   reg [9:0] \o_encoded$next ;
  1710.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:17" *)
  1711.   wire [3:0] ones;
  1712.   (* src = "top_vgatest.py:101" *)
  1713.   input pixel_clk;
  1714.   (* src = "top_vgatest.py:101" *)
  1715.   input pixel_rst;
  1716.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:16" *)
  1717.   wire [8:0] xnored;
  1718.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:15" *)
  1719.   wire [8:0] xored;
  1720.   assign \$9  = i_data[5] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:29" *) xored[4];
  1721.   assign \$99  = \$97  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[7];
  1722.   assign \$101  = dc_bias == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) 1'h0;
  1723.   assign \$103  = data_word_disparity == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) 1'h0;
  1724.   assign \$105  = \$101  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) \$103 ;
  1725.   assign \$107  = dc_bias[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) 1'h0;
  1726.   assign \$109  = data_word_disparity[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) 1'h0;
  1727.   assign \$111  = \$107  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) \$109 ;
  1728.   assign \$113  = dc_bias[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) 1'h1;
  1729.   assign \$115  = data_word_disparity[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) 1'h1;
  1730.   assign \$117  = \$113  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) \$115 ;
  1731.   assign \$11  = i_data[6] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:30" *) xored[5];
  1732.   assign \$119  = \$111  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) \$117 ;
  1733.   assign \$121  = + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:97" *) { 1'h1, data_word[7:0] };
  1734.   assign \$123  = dc_bias == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) 1'h0;
  1735.   assign \$125  = data_word_disparity == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) 1'h0;
  1736.   assign \$127  = \$123  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *) \$125 ;
  1737.   assign \$129  = dc_bias[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) 1'h0;
  1738.   assign \$131  = data_word_disparity[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) 1'h0;
  1739.   assign \$133  = \$129  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) \$131 ;
  1740.   assign \$135  = dc_bias[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) 1'h1;
  1741.   assign \$137  = data_word_disparity[3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) 1'h1;
  1742.   assign \$13  = i_data[7] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:31" *) xored[6];
  1743.   assign \$139  = \$135  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:103" *) \$137 ;
  1744.   assign \$141  = \$133  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" *) \$139 ;
  1745.   assign \$144  = dc_bias + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:98" *) data_word_disparity;
  1746.   assign \$147  = dc_bias - (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:101" *) data_word_disparity;
  1747.   assign \$150  = dc_bias + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:105" *) data_word[8];
  1748.   assign \$152  = \$150  - (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:105" *) data_word_disparity;
  1749.   assign \$155  = dc_bias - (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:108" *) data_word_inv[8];
  1750.   assign \$157  = \$155  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:108" *) data_word_disparity;
  1751.   assign \$16  = i_data[1] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:37" *) xnored[0];
  1752.   assign \$15  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:37" *) \$16 ;
  1753.   assign \$1  = i_data[1] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:25" *) xored[0];
  1754.   assign \$20  = i_data[2] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:38" *) xnored[1];
  1755.   assign \$19  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:38" *) \$20 ;
  1756.   assign \$24  = i_data[3] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:39" *) xnored[2];
  1757.   assign \$23  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:39" *) \$24 ;
  1758.   assign \$28  = i_data[4] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:40" *) xnored[3];
  1759.   assign \$27  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:40" *) \$28 ;
  1760.   assign \$32  = i_data[5] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:41" *) xnored[4];
  1761.   assign \$31  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:41" *) \$32 ;
  1762.   assign \$36  = i_data[6] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:42" *) xnored[5];
  1763.   assign \$35  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:42" *) \$36 ;
  1764.   assign \$3  = i_data[2] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:26" *) xored[1];
  1765.   assign \$40  = i_data[7] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:43" *) xnored[6];
  1766.   assign \$39  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:43" *) \$40 ;
  1767.   assign \$44  = 1'h0 + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[0];
  1768.   assign \$46  = \$44  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[1];
  1769.   assign \$48  = \$46  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[2];
  1770.   assign \$50  = \$48  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[3];
  1771.   assign \$52  = \$50  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[4];
  1772.   assign \$54  = \$52  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[5];
  1773.   assign \$56  = \$54  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[6];
  1774.   assign \$58  = \$56  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:49" *) i_data[7];
  1775.   assign \$5  = i_data[3] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:27" *) xored[2];
  1776.   assign \$60  = ones > (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 3'h4;
  1777.   assign \$62  = ones == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 3'h4;
  1778.   assign \$64  = i_data[0] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 1'h0;
  1779.   assign \$66  = \$62  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) \$64 ;
  1780.   assign \$68  = \$60  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) \$66 ;
  1781.   assign \$70  = ones > (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 3'h4;
  1782.   assign \$72  = ones == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 3'h4;
  1783.   assign \$74  = i_data[0] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) 1'h0;
  1784.   assign \$76  = \$72  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) \$74 ;
  1785.   assign \$78  = \$70  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *) \$76 ;
  1786.   assign \$7  = i_data[4] ^ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:28" *) xored[3];
  1787.   assign \$80  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:63" *) xnored;
  1788.   assign \$82  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:66" *) xored;
  1789.   assign \$85  = 4'hc + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[0];
  1790.   assign \$87  = \$85  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[1];
  1791.   assign \$89  = \$87  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[2];
  1792.   assign \$91  = \$89  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[3];
  1793.   assign \$93  = \$91  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[4];
  1794.   assign \$95  = \$93  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[5];
  1795.   assign \$97  = \$95  + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:70" *) data_word[6];
  1796.   always @(posedge pixel_clk)
  1797.       dc_bias <= \dc_bias$next ;
  1798.   always @(posedge pixel_clk)
  1799.       o_encoded <= \o_encoded$next ;
  1800.   always @* begin
  1801.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1802.     casez (\$68 )
  1803.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" */
  1804.       1'h1:
  1805.           data_word = xnored;
  1806.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:64" */
  1807.       default:
  1808.           data_word = xored;
  1809.     endcase
  1810.   end
  1811.   always @* begin
  1812.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" *)
  1813.     casez (\$78 )
  1814.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:61" */
  1815.       1'h1:
  1816.           data_word_inv = \$80 ;
  1817.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:64" */
  1818.       default:
  1819.           data_word_inv = \$82 ;
  1820.     endcase
  1821.   end
  1822.   always @* begin
  1823.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:82" *)
  1824.     casez (i_blank)
  1825.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:82" */
  1826.       1'h1:
  1827.           (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:83" *)
  1828.           casez (i_c)
  1829.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:84" */
  1830.             2'h0:
  1831.                 \o_encoded$next  = 10'h354;
  1832.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:86" */
  1833.             2'h1:
  1834.                 \o_encoded$next  = 10'h0ab;
  1835.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:88" */
  1836.             2'h2:
  1837.                 \o_encoded$next  = 10'h154;
  1838.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:90" */
  1839.             default:
  1840.                 \o_encoded$next  = 10'h2ab;
  1841.           endcase
  1842.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:93" */
  1843.       default:
  1844.           (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1845.           casez ({ \$119 , \$105  })
  1846.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" */
  1847.             2'b?1:
  1848.                 (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:96" *)
  1849.                 casez (data_word[8])
  1850.                   /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:96" */
  1851.                   1'h1:
  1852.                       \o_encoded$next  = \$121 ;
  1853.                   /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:99" */
  1854.                   default:
  1855.                       \o_encoded$next  = { 2'h2, data_word_inv[7:0] };
  1856.                 endcase
  1857.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" */
  1858.             2'b1?:
  1859.                 \o_encoded$next  = { 1'h1, data_word[8], data_word_inv[7:0] };
  1860.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:106" */
  1861.             default:
  1862.                 \o_encoded$next  = { 1'h0, data_word };
  1863.           endcase
  1864.     endcase
  1865.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  1866.     casez (pixel_rst)
  1867.       1'h1:
  1868.           \o_encoded$next  = 10'h000;
  1869.     endcase
  1870.   end
  1871.   always @* begin
  1872.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:82" *)
  1873.     casez (i_blank)
  1874.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:82" */
  1875.       1'h1:
  1876.           \dc_bias$next  = 4'h0;
  1877.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:93" */
  1878.       default:
  1879.           (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" *)
  1880.           casez ({ \$141 , \$127  })
  1881.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:94" */
  1882.             2'b?1:
  1883.                 (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:96" *)
  1884.                 casez (data_word[8])
  1885.                   /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:96" */
  1886.                   1'h1:
  1887.                       \dc_bias$next  = \$143 [3:0];
  1888.                   /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:99" */
  1889.                   default:
  1890.                       \dc_bias$next  = \$146 [3:0];
  1891.                 endcase
  1892.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:102" */
  1893.             2'b1?:
  1894.                 \dc_bias$next  = \$149 [3:0];
  1895.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:106" */
  1896.             default:
  1897.                 \dc_bias$next  = \$154 [3:0];
  1898.           endcase
  1899.     endcase
  1900.   end
  1901.   assign \$43  = \$58 ;
  1902.   assign \$84  = \$99 ;
  1903.   assign \$143  = \$144 ;
  1904.   assign \$146  = \$147 ;
  1905.   assign \$149  = \$152 ;
  1906.   assign \$154  = \$157 ;
  1907.   assign data_word_disparity = \$99 [3:0];
  1908.   assign ones = \$58 [3:0];
  1909.   assign xnored[8] = 1'h0;
  1910.   assign xnored[7] = \$39 ;
  1911.   assign xnored[6] = \$35 ;
  1912.   assign xnored[5] = \$31 ;
  1913.   assign xnored[4] = \$27 ;
  1914.   assign xnored[3] = \$23 ;
  1915.   assign xnored[2] = \$19 ;
  1916.   assign xnored[1] = \$15 ;
  1917.   assign xnored[0] = i_data[0];
  1918.   assign xored[8] = 1'h1;
  1919.   assign xored[7] = \$13 ;
  1920.   assign xored[6] = \$11 ;
  1921.   assign xored[5] = \$9 ;
  1922.   assign xored[4] = \$7 ;
  1923.   assign xored[3] = \$5 ;
  1924.   assign xored[2] = \$3 ;
  1925.   assign xored[1] = \$1 ;
  1926.   assign xored[0] = i_data[0];
  1927. endmodule
  1928.  
  1929. (* \nmigen.hierarchy  = "top.top.vga" *)
  1930. (* generator = "nMigen" *)
  1931. module vga(o_vga_r, o_vga_g, o_vga_b, o_vga_hsync, o_vga_vsync, o_vga_blank, pixel_rst, pixel_clk, i_clk_en);
  1932.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:98" *)
  1933.   wire \$1 ;
  1934.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:104" *)
  1935.   wire [16:0] \$10 ;
  1936.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:104" *)
  1937.   wire [16:0] \$11 ;
  1938.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:119" *)
  1939.   wire \$13 ;
  1940.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:124" *)
  1941.   wire \$15 ;
  1942.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:119" *)
  1943.   wire \$17 ;
  1944.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:124" *)
  1945.   wire \$19 ;
  1946.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:129" *)
  1947.   wire \$21 ;
  1948.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:131" *)
  1949.   wire \$23 ;
  1950.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:134" *)
  1951.   wire \$25 ;
  1952.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:139" *)
  1953.   wire \$27 ;
  1954.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:134" *)
  1955.   wire \$29 ;
  1956.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:106" *)
  1957.   wire [16:0] \$3 ;
  1958.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:139" *)
  1959.   wire \$31 ;
  1960.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:144" *)
  1961.   wire \$33 ;
  1962.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:146" *)
  1963.   wire \$35 ;
  1964.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:152" *)
  1965.   wire [7:0] \$37 ;
  1966.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:153" *)
  1967.   wire \$38 ;
  1968.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:106" *)
  1969.   wire [16:0] \$4 ;
  1970.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:153" *)
  1971.   wire \$40 ;
  1972.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:153" *)
  1973.   wire \$42 ;
  1974.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:155" *)
  1975.   wire [7:0] \$45 ;
  1976.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:156" *)
  1977.   wire \$46 ;
  1978.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:158" *)
  1979.   wire [7:0] \$49 ;
  1980.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:158" *)
  1981.   wire [7:0] \$50 ;
  1982.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:159" *)
  1983.   wire [1:0] \$51 ;
  1984.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:159" *)
  1985.   wire \$53 ;
  1986.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:172" *)
  1987.   wire [5:0] \$56 ;
  1988.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:172" *)
  1989.   wire [7:0] \$58 ;
  1990.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:98" *)
  1991.   wire \$6 ;
  1992.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:172" *)
  1993.   wire [7:0] \$60 ;
  1994.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:172" *)
  1995.   wire [7:0] \$62 ;
  1996.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:173" *)
  1997.   wire [7:0] \$64 ;
  1998.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:173" *)
  1999.   wire [7:0] \$66 ;
  2000.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:173" *)
  2001.   wire [7:0] \$68 ;
  2002.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:173" *)
  2003.   wire [7:0] \$70 ;
  2004.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:174" *)
  2005.   wire [7:0] \$72 ;
  2006.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:174" *)
  2007.   wire [7:0] \$74 ;
  2008.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:101" *)
  2009.   wire \$8 ;
  2010.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:93" *)
  2011.   wire [7:0] A;
  2012.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:77" *)
  2013.   reg [15:0] CounterX = 16'h0000;
  2014.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:77" *)
  2015.   reg [15:0] \CounterX$next ;
  2016.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:78" *)
  2017.   reg [15:0] CounterY = 16'h0000;
  2018.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:78" *)
  2019.   reg [15:0] \CounterY$next ;
  2020.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:81" *)
  2021.   reg R_blank = 1'h0;
  2022.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:81" *)
  2023.   reg \R_blank$next ;
  2024.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:85" *)
  2025.   reg R_blank_early = 1'h0;
  2026.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:85" *)
  2027.   reg \R_blank_early$next ;
  2028.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:82" *)
  2029.   reg R_disp = 1'h0;
  2030.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:82" *)
  2031.   reg \R_disp$next ;
  2032.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:83" *)
  2033.   reg R_disp_early = 1'h0;
  2034.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:83" *)
  2035.   reg \R_disp_early$next ;
  2036.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:87" *)
  2037.   reg R_fetch_next = 1'h0;
  2038.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:87" *)
  2039.   reg \R_fetch_next$next ;
  2040.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:79" *)
  2041.   reg R_hsync = 1'h0;
  2042.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:79" *)
  2043.   reg \R_hsync$next ;
  2044.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:86" *)
  2045.   reg R_vblank = 1'h0;
  2046.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:86" *)
  2047.   reg \R_vblank$next ;
  2048.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:84" *)
  2049.   reg R_vdisp = 1'h0;
  2050.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:84" *)
  2051.   reg \R_vdisp$next ;
  2052.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:90" *)
  2053.   reg [7:0] R_vga_b = 8'h00;
  2054.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:90" *)
  2055.   reg [7:0] \R_vga_b$next ;
  2056.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:89" *)
  2057.   reg [7:0] R_vga_g = 8'h00;
  2058.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:89" *)
  2059.   reg [7:0] \R_vga_g$next ;
  2060.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:88" *)
  2061.   reg [7:0] R_vga_r = 8'h00;
  2062.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:88" *)
  2063.   reg [7:0] \R_vga_r$next ;
  2064.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:80" *)
  2065.   reg R_vsync = 1'h0;
  2066.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:80" *)
  2067.   reg \R_vsync$next ;
  2068.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:94" *)
  2069.   wire [7:0] T;
  2070.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:92" *)
  2071.   wire [7:0] W;
  2072.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:95" *)
  2073.   wire [5:0] Z;
  2074.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:29" *)
  2075.   input i_clk_en;
  2076.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:35" *)
  2077.   wire [15:0] o_beam_x;
  2078.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:36" *)
  2079.   wire [15:0] o_beam_y;
  2080.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:34" *)
  2081.   wire o_fetch_next;
  2082.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:39" *)
  2083.   output [7:0] o_vga_b;
  2084.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:43" *)
  2085.   output o_vga_blank;
  2086.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:44" *)
  2087.   wire o_vga_de;
  2088.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:38" *)
  2089.   output [7:0] o_vga_g;
  2090.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:40" *)
  2091.   output o_vga_hsync;
  2092.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:37" *)
  2093.   output [7:0] o_vga_r;
  2094.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:41" *)
  2095.   output o_vga_vsync;
  2096.   (* src = "top_vgatest.py:101" *)
  2097.   input pixel_clk;
  2098.   (* src = "top_vgatest.py:101" *)
  2099.   input pixel_rst;
  2100.   assign \$11  = CounterY + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:104" *) 1'h1;
  2101.   assign \$13  = CounterX == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:119" *) 16'h04ff;
  2102.   assign \$15  = CounterX == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:124" *) 16'h059f;
  2103.   assign \$17  = CounterX == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:119" *) 16'h04ff;
  2104.   assign \$1  = CounterX == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:98" *) 16'h059f;
  2105.   assign \$19  = CounterX == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:124" *) 16'h059f;
  2106.   assign \$21  = CounterX == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:129" *) 16'h052f;
  2107.   assign \$23  = CounterX == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:131" *) 16'h054f;
  2108.   assign \$25  = CounterY == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:134" *) 16'h031f;
  2109.   assign \$27  = CounterY == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:139" *) 16'h0336;
  2110.   assign \$29  = CounterY == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:134" *) 16'h031f;
  2111.   assign \$31  = CounterY == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:139" *) 16'h0336;
  2112.   assign \$33  = CounterY == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:144" *) 16'h0322;
  2113.   assign \$35  = CounterY == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:146" *) 16'h0328;
  2114.   assign \$38  = CounterX[7:5] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:153" *) 2'h2;
  2115.   assign \$40  = CounterY[7:5] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:153" *) 2'h2;
  2116.   assign \$42  = \$38  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:153" *) \$40 ;
  2117.   assign \$37  = \$42  ? (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:152" *) 8'hff : 8'h00;
  2118.   assign \$46  = CounterX[7:0] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:156" *) CounterY[7:0];
  2119.   assign \$45  = \$46  ? (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:155" *) 8'hff : 8'h00;
  2120.   assign \$4  = CounterX + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:106" *) 1'h1;
  2121.   assign \$51  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:159" *) CounterX[4:3];
  2122.   assign \$53  = CounterY[4:3] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:159" *) \$51 ;
  2123.   assign \$50  = \$53  ? (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:158" *) 8'hff : 8'h00;
  2124.   assign \$56  = CounterX[5:0] & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:172" *) Z;
  2125.   assign \$58  = { \$56 , 1'h0 } | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:172" *) W;
  2126.   assign \$60  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:172" *) A;
  2127.   assign \$62  = \$58  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:172" *) \$60 ;
  2128.   assign \$64  = CounterX[7:0] & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:173" *) T;
  2129.   assign \$66  = \$64  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:173" *) W;
  2130.   assign \$68  = ~ (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:173" *) A;
  2131.   assign \$6  = CounterX == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:98" *) 16'h059f;
  2132.   assign \$70  = \$66  & (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:173" *) \$68 ;
  2133.   assign \$72  = CounterY[7:0] | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:174" *) W;
  2134.   assign \$74  = \$72  | (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:174" *) A;
  2135.   assign \$8  = CounterY == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:101" *) 16'h0336;
  2136.   always @(posedge pixel_clk)
  2137.       R_disp <= \R_disp$next ;
  2138.   always @(posedge pixel_clk)
  2139.       R_blank <= \R_blank$next ;
  2140.   always @(posedge pixel_clk)
  2141.       R_vga_b <= \R_vga_b$next ;
  2142.   always @(posedge pixel_clk)
  2143.       R_vga_g <= \R_vga_g$next ;
  2144.   always @(posedge pixel_clk)
  2145.       R_vga_r <= \R_vga_r$next ;
  2146.   always @(posedge pixel_clk)
  2147.       R_vsync <= \R_vsync$next ;
  2148.   always @(posedge pixel_clk)
  2149.       R_vdisp <= \R_vdisp$next ;
  2150.   always @(posedge pixel_clk)
  2151.       R_vblank <= \R_vblank$next ;
  2152.   always @(posedge pixel_clk)
  2153.       R_hsync <= \R_hsync$next ;
  2154.   always @(posedge pixel_clk)
  2155.       R_disp_early <= \R_disp_early$next ;
  2156.   always @(posedge pixel_clk)
  2157.       R_blank_early <= \R_blank_early$next ;
  2158.   always @(posedge pixel_clk)
  2159.       R_fetch_next <= \R_fetch_next$next ;
  2160.   always @(posedge pixel_clk)
  2161.       CounterY <= \CounterY$next ;
  2162.   always @(posedge pixel_clk)
  2163.       CounterX <= \CounterX$next ;
  2164.   always @* begin
  2165.     \CounterX$next  = CounterX;
  2166.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:97" *)
  2167.     casez (i_clk_en)
  2168.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:97" */
  2169.       1'h1:
  2170.           (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:98" *)
  2171.           casez (\$1 )
  2172.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:98" */
  2173.             1'h1:
  2174.                 \CounterX$next  = 16'h0000;
  2175.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:105" */
  2176.             default:
  2177.                 \CounterX$next  = \$3 [15:0];
  2178.           endcase
  2179.     endcase
  2180.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2181.     casez (pixel_rst)
  2182.       1'h1:
  2183.           \CounterX$next  = 16'h0000;
  2184.     endcase
  2185.   end
  2186.   always @* begin
  2187.     \CounterY$next  = CounterY;
  2188.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:97" *)
  2189.     casez (i_clk_en)
  2190.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:97" */
  2191.       1'h1:
  2192.           (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:98" *)
  2193.           casez (\$6 )
  2194.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:98" */
  2195.             1'h1:
  2196.                 (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:101" *)
  2197.                 casez (\$8 )
  2198.                   /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:101" */
  2199.                   1'h1:
  2200.                       \CounterY$next  = 16'h0000;
  2201.                   /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:103" */
  2202.                   default:
  2203.                       \CounterY$next  = \$10 [15:0];
  2204.                 endcase
  2205.           endcase
  2206.     endcase
  2207.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2208.     casez (pixel_rst)
  2209.       1'h1:
  2210.           \CounterY$next  = 16'h0000;
  2211.     endcase
  2212.   end
  2213.   always @* begin
  2214.     \R_vdisp$next  = R_vdisp;
  2215.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:134" *)
  2216.     casez ({ \$31 , \$29  })
  2217.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:134" */
  2218.       2'b?1:
  2219.           \R_vdisp$next  = 1'h0;
  2220.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:139" */
  2221.       2'b1?:
  2222.           \R_vdisp$next  = 1'h1;
  2223.     endcase
  2224.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2225.     casez (pixel_rst)
  2226.       1'h1:
  2227.           \R_vdisp$next  = 1'h0;
  2228.     endcase
  2229.   end
  2230.   always @* begin
  2231.     \R_vsync$next  = R_vsync;
  2232.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:144" *)
  2233.     casez ({ \$35 , \$33  })
  2234.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:144" */
  2235.       2'b?1:
  2236.           \R_vsync$next  = 1'h1;
  2237.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:146" */
  2238.       2'b1?:
  2239.           \R_vsync$next  = 1'h0;
  2240.     endcase
  2241.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2242.     casez (pixel_rst)
  2243.       1'h1:
  2244.           \R_vsync$next  = 1'h0;
  2245.     endcase
  2246.   end
  2247.   always @* begin
  2248.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:164" *)
  2249.     casez (R_blank)
  2250.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:164" */
  2251.       1'h1:
  2252.           \R_vga_r$next  = 8'h00;
  2253.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:170" */
  2254.       default:
  2255.           \R_vga_r$next  = \$62 ;
  2256.     endcase
  2257.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2258.     casez (pixel_rst)
  2259.       1'h1:
  2260.           \R_vga_r$next  = 8'h00;
  2261.     endcase
  2262.   end
  2263.   always @* begin
  2264.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:164" *)
  2265.     casez (R_blank)
  2266.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:164" */
  2267.       1'h1:
  2268.           \R_vga_g$next  = 8'h00;
  2269.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:170" */
  2270.       default:
  2271.           \R_vga_g$next  = \$70 ;
  2272.     endcase
  2273.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2274.     casez (pixel_rst)
  2275.       1'h1:
  2276.           \R_vga_g$next  = 8'h00;
  2277.     endcase
  2278.   end
  2279.   always @* begin
  2280.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:164" *)
  2281.     casez (R_blank)
  2282.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:164" */
  2283.       1'h1:
  2284.           \R_vga_b$next  = 8'h00;
  2285.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:170" */
  2286.       default:
  2287.           \R_vga_b$next  = \$74 ;
  2288.     endcase
  2289.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2290.     casez (pixel_rst)
  2291.       1'h1:
  2292.           \R_vga_b$next  = 8'h00;
  2293.     endcase
  2294.   end
  2295.   always @* begin
  2296.     \R_blank$next  = R_blank_early;
  2297.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2298.     casez (pixel_rst)
  2299.       1'h1:
  2300.           \R_blank$next  = 1'h0;
  2301.     endcase
  2302.   end
  2303.   always @* begin
  2304.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:97" *)
  2305.     casez (i_clk_en)
  2306.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:97" */
  2307.       1'h1:
  2308.           \R_fetch_next$next  = R_disp_early;
  2309.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:109" */
  2310.       default:
  2311.           \R_fetch_next$next  = 1'h0;
  2312.     endcase
  2313.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2314.     casez (pixel_rst)
  2315.       1'h1:
  2316.           \R_fetch_next$next  = 1'h0;
  2317.     endcase
  2318.   end
  2319.   always @* begin
  2320.     \R_disp$next  = R_disp_early;
  2321.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2322.     casez (pixel_rst)
  2323.       1'h1:
  2324.           \R_disp$next  = 1'h0;
  2325.     endcase
  2326.   end
  2327.   always @* begin
  2328.     \R_blank_early$next  = R_blank_early;
  2329.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:119" *)
  2330.     casez ({ \$15 , \$13  })
  2331.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:119" */
  2332.       2'b?1:
  2333.           \R_blank_early$next  = 1'h1;
  2334.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:124" */
  2335.       2'b1?:
  2336.           \R_blank_early$next  = R_vblank;
  2337.     endcase
  2338.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2339.     casez (pixel_rst)
  2340.       1'h1:
  2341.           \R_blank_early$next  = 1'h0;
  2342.     endcase
  2343.   end
  2344.   always @* begin
  2345.     \R_disp_early$next  = R_disp_early;
  2346.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:119" *)
  2347.     casez ({ \$19 , \$17  })
  2348.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:119" */
  2349.       2'b?1:
  2350.           \R_disp_early$next  = 1'h0;
  2351.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:124" */
  2352.       2'b1?:
  2353.           \R_disp_early$next  = R_vdisp;
  2354.     endcase
  2355.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2356.     casez (pixel_rst)
  2357.       1'h1:
  2358.           \R_disp_early$next  = 1'h0;
  2359.     endcase
  2360.   end
  2361.   always @* begin
  2362.     \R_hsync$next  = R_hsync;
  2363.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:129" *)
  2364.     casez ({ \$23 , \$21  })
  2365.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:129" */
  2366.       2'b?1:
  2367.           \R_hsync$next  = 1'h1;
  2368.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:131" */
  2369.       2'b1?:
  2370.           \R_hsync$next  = 1'h0;
  2371.     endcase
  2372.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2373.     casez (pixel_rst)
  2374.       1'h1:
  2375.           \R_hsync$next  = 1'h0;
  2376.     endcase
  2377.   end
  2378.   always @* begin
  2379.     \R_vblank$next  = R_vblank;
  2380.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:134" *)
  2381.     casez ({ \$27 , \$25  })
  2382.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:134" */
  2383.       2'b?1:
  2384.           \R_vblank$next  = 1'h1;
  2385.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga.py:139" */
  2386.       2'b1?:
  2387.           \R_vblank$next  = 1'h0;
  2388.     endcase
  2389.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2390.     casez (pixel_rst)
  2391.       1'h1:
  2392.           \R_vblank$next  = 1'h0;
  2393.     endcase
  2394.   end
  2395.   assign \$3  = \$4 ;
  2396.   assign \$10  = \$11 ;
  2397.   assign \$49  = \$50 ;
  2398.   assign o_vga_de = R_disp;
  2399.   assign o_vga_blank = R_blank;
  2400.   assign o_vga_vsync = R_vsync;
  2401.   assign o_vga_hsync = R_hsync;
  2402.   assign o_vga_b = R_vga_b;
  2403.   assign o_vga_g = R_vga_g;
  2404.   assign o_vga_r = R_vga_r;
  2405.   assign T = { CounterY[6], CounterY[6], CounterY[6], CounterY[6], CounterY[6], CounterY[6], CounterY[6], CounterY[6] };
  2406.   assign Z = \$50 [5:0];
  2407.   assign W = \$45 ;
  2408.   assign A = \$37 ;
  2409.   assign o_fetch_next = R_fetch_next;
  2410.   assign o_beam_y = CounterY;
  2411.   assign o_beam_x = CounterX;
  2412. endmodule
  2413.  
  2414. (* \nmigen.hierarchy  = "top.top.vga2dvid" *)
  2415. (* generator = "nMigen" *)
  2416. module vga2dvid(i_green, i_blue, i_hsync, i_vsync, i_blank, o_clk, o_red, o_green, o_blue, pixel_rst, pixel_clk, shift_clk, i_red);
  2417.   wire [4:0] \$1 ;
  2418.   wire [4:0] \$11 ;
  2419.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:155" *)
  2420.   wire \$12 ;
  2421.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:165" *)
  2422.   wire [9:0] \$14 ;
  2423.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:168" *)
  2424.   wire \$16 ;
  2425.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:168" *)
  2426.   wire \$18 ;
  2427.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:155" *)
  2428.   wire \$2 ;
  2429.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:177" *)
  2430.   wire [7:0] \$20 ;
  2431.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:177" *)
  2432.   wire [7:0] \$21 ;
  2433.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:163" *)
  2434.   wire [9:0] \$4 ;
  2435.   wire [4:0] \$6 ;
  2436.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:155" *)
  2437.   wire \$7 ;
  2438.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:164" *)
  2439.   wire [9:0] \$9 ;
  2440.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:59" *)
  2441.   wire [7:0] R_shift_clock_synchronizer;
  2442.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:60" *)
  2443.   reg [6:0] R_sync_fail = 7'h00;
  2444.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:60" *)
  2445.   reg [6:0] \R_sync_fail$next ;
  2446.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:65" *)
  2447.   wire [7:0] blue_d;
  2448.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:61" *)
  2449.   wire [1:0] c_blue;
  2450.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:47" *)
  2451.   wire [9:0] encoded_blue;
  2452.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:46" *)
  2453.   wire [9:0] encoded_green;
  2454.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:45" *)
  2455.   wire [9:0] encoded_red;
  2456.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:64" *)
  2457.   wire [7:0] green_d;
  2458.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:17" *)
  2459.   input i_blank;
  2460.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:16" *)
  2461.   input [7:0] i_blue;
  2462.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:15" *)
  2463.   input [7:0] i_green;
  2464.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:18" *)
  2465.   input i_hsync;
  2466.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:14" *)
  2467.   input [7:0] i_red;
  2468.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:19" *)
  2469.   input i_vsync;
  2470.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:51" *)
  2471.   reg [9:0] latched_blue = 10'h000;
  2472.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:51" *)
  2473.   reg [9:0] \latched_blue$next ;
  2474.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:50" *)
  2475.   reg [9:0] latched_green = 10'h000;
  2476.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:50" *)
  2477.   reg [9:0] \latched_green$next ;
  2478.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:49" *)
  2479.   reg [9:0] latched_red = 10'h000;
  2480.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:49" *)
  2481.   reg [9:0] \latched_red$next ;
  2482.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:27" *)
  2483.   output [1:0] o_blue;
  2484.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:23" *)
  2485.   wire [9:0] o_blue_par;
  2486.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:28" *)
  2487.   output [1:0] o_clk;
  2488.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:26" *)
  2489.   output [1:0] o_green;
  2490.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:22" *)
  2491.   wire [9:0] o_green_par;
  2492.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:25" *)
  2493.   output [1:0] o_red;
  2494.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:21" *)
  2495.   wire [9:0] o_red_par;
  2496.   (* src = "top_vgatest.py:101" *)
  2497.   input pixel_clk;
  2498.   (* src = "top_vgatest.py:101" *)
  2499.   input pixel_rst;
  2500.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:63" *)
  2501.   wire [7:0] red_d;
  2502.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:55" *)
  2503.   reg [9:0] shift_blue = 10'h000;
  2504.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:55" *)
  2505.   reg [9:0] \shift_blue$next ;
  2506.   (* src = "top_vgatest.py:102" *)
  2507.   input shift_clk;
  2508.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:57" *)
  2509.   reg [9:0] shift_clock = 10'h01f;
  2510.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:57" *)
  2511.   reg [9:0] \shift_clock$next ;
  2512.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:54" *)
  2513.   reg [9:0] shift_green = 10'h000;
  2514.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:54" *)
  2515.   reg [9:0] \shift_green$next ;
  2516.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:53" *)
  2517.   reg [9:0] shift_red = 10'h000;
  2518.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:53" *)
  2519.   reg [9:0] \shift_red$next ;
  2520.   (* src = "top_vgatest.py:102" *)
  2521.   wire shift_rst;
  2522.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:9" *)
  2523.   wire u21_i_blank;
  2524.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:8" *)
  2525.   wire [1:0] u21_i_c;
  2526.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:7" *)
  2527.   wire [7:0] u21_i_data;
  2528.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:10" *)
  2529.   wire [9:0] u21_o_encoded;
  2530.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:9" *)
  2531.   wire u22_i_blank;
  2532.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:8" *)
  2533.   wire [1:0] u22_i_c;
  2534.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:7" *)
  2535.   wire [7:0] u22_i_data;
  2536.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:10" *)
  2537.   wire [9:0] u22_o_encoded;
  2538.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:9" *)
  2539.   wire u23_i_blank;
  2540.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:8" *)
  2541.   wire [1:0] u23_i_c;
  2542.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:7" *)
  2543.   wire [7:0] u23_i_data;
  2544.   (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/tmds_encoder.py:10" *)
  2545.   wire [9:0] u23_o_encoded;
  2546.   assign \$9  = + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:164" *) { 1'h0, shift_green[9:2] };
  2547.   assign \$12  = shift_clock[5:4] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:155" *) \$11 [4];
  2548.   assign \$14  = + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:165" *) { 1'h0, shift_blue[9:2] };
  2549.   assign \$16  = R_shift_clock_synchronizer[7] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:168" *) 1'h0;
  2550.   assign \$18  = R_shift_clock_synchronizer[7] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:168" *) 1'h0;
  2551.   assign \$21  = R_sync_fail + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:177" *) 1'h1;
  2552.   assign \$2  = shift_clock[5:4] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:155" *) \$1 [4];
  2553.   assign \$4  = + (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:163" *) { 1'h0, shift_red[9:2] };
  2554.   assign \$7  = shift_clock[5:4] == (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:155" *) \$6 [4];
  2555.   always @(posedge pixel_clk)
  2556.       latched_red <= \latched_red$next ;
  2557.   always @(posedge shift_clk)
  2558.       R_sync_fail <= \R_sync_fail$next ;
  2559.   always @(posedge shift_clk)
  2560.       shift_clock <= \shift_clock$next ;
  2561.   always @(posedge shift_clk)
  2562.       shift_blue <= \shift_blue$next ;
  2563.   always @(posedge shift_clk)
  2564.       shift_green <= \shift_green$next ;
  2565.   always @(posedge shift_clk)
  2566.       shift_red <= \shift_red$next ;
  2567.   always @(posedge pixel_clk)
  2568.       latched_blue <= \latched_blue$next ;
  2569.   always @(posedge pixel_clk)
  2570.       latched_green <= \latched_green$next ;
  2571.   u21 u21 (
  2572.     .i_blank(u21_i_blank),
  2573.     .i_c(u21_i_c),
  2574.     .i_data(u21_i_data),
  2575.     .o_encoded(u21_o_encoded),
  2576.     .pixel_clk(pixel_clk),
  2577.     .pixel_rst(pixel_rst)
  2578.   );
  2579.   u22 u22 (
  2580.     .i_blank(u22_i_blank),
  2581.     .i_c(u22_i_c),
  2582.     .i_data(u22_i_data),
  2583.     .o_encoded(u22_o_encoded),
  2584.     .pixel_clk(pixel_clk),
  2585.     .pixel_rst(pixel_rst)
  2586.   );
  2587.   u23 u23 (
  2588.     .i_blank(u23_i_blank),
  2589.     .i_c(u23_i_c),
  2590.     .i_data(u23_i_data),
  2591.     .o_encoded(u23_o_encoded),
  2592.     .pixel_clk(pixel_clk),
  2593.     .pixel_rst(pixel_rst)
  2594.   );
  2595.   always @* begin
  2596.     \latched_red$next  = encoded_red;
  2597.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2598.     casez (pixel_rst)
  2599.       1'h1:
  2600.           \latched_red$next  = 10'h000;
  2601.     endcase
  2602.   end
  2603.   always @* begin
  2604.     \latched_green$next  = encoded_green;
  2605.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2606.     casez (pixel_rst)
  2607.       1'h1:
  2608.           \latched_green$next  = 10'h000;
  2609.     endcase
  2610.   end
  2611.   always @* begin
  2612.     \latched_blue$next  = encoded_blue;
  2613.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2614.     casez (pixel_rst)
  2615.       1'h1:
  2616.           \latched_blue$next  = 10'h000;
  2617.     endcase
  2618.   end
  2619.   always @* begin
  2620.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:155" *)
  2621.     casez (\$2 )
  2622.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:155" */
  2623.       1'h1:
  2624.           \shift_red$next  = latched_red;
  2625.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:161" */
  2626.       default:
  2627.           \shift_red$next  = \$4 ;
  2628.     endcase
  2629.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2630.     casez (shift_rst)
  2631.       1'h1:
  2632.           \shift_red$next  = 10'h000;
  2633.     endcase
  2634.   end
  2635.   always @* begin
  2636.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:155" *)
  2637.     casez (\$7 )
  2638.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:155" */
  2639.       1'h1:
  2640.           \shift_green$next  = latched_green;
  2641.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:161" */
  2642.       default:
  2643.           \shift_green$next  = \$9 ;
  2644.     endcase
  2645.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2646.     casez (shift_rst)
  2647.       1'h1:
  2648.           \shift_green$next  = 10'h000;
  2649.     endcase
  2650.   end
  2651.   always @* begin
  2652.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:155" *)
  2653.     casez (\$12 )
  2654.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:155" */
  2655.       1'h1:
  2656.           \shift_blue$next  = latched_blue;
  2657.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:161" */
  2658.       default:
  2659.           \shift_blue$next  = \$14 ;
  2660.     endcase
  2661.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2662.     casez (shift_rst)
  2663.       1'h1:
  2664.           \shift_blue$next  = 10'h000;
  2665.     endcase
  2666.   end
  2667.   always @* begin
  2668.     \shift_clock$next  = shift_clock;
  2669.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:168" *)
  2670.     casez (\$16 )
  2671.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:168" */
  2672.       1'h1:
  2673.           \shift_clock$next  = { shift_clock[1:0], shift_clock[9:2] };
  2674.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:170" */
  2675.       default:
  2676.           (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:173" *)
  2677.           casez (R_sync_fail[6])
  2678.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:173" */
  2679.             1'h1:
  2680.                 \shift_clock$next  = 10'h01f;
  2681.           endcase
  2682.     endcase
  2683.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2684.     casez (shift_rst)
  2685.       1'h1:
  2686.           \shift_clock$next  = 10'h01f;
  2687.     endcase
  2688.   end
  2689.   always @* begin
  2690.     \R_sync_fail$next  = R_sync_fail;
  2691.     (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:168" *)
  2692.     casez (\$18 )
  2693.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:168" */
  2694.       1'h1:
  2695.           /* empty */;
  2696.       /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:170" */
  2697.       default:
  2698.           (* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:173" *)
  2699.           casez (R_sync_fail[6])
  2700.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:173" */
  2701.             1'h1:
  2702.                 \R_sync_fail$next  = 7'h00;
  2703.             /* src = "/home/oguz286/Projects/FPGA/nmigen/ulx3s/dvi/vga2dvid.py:176" */
  2704.             default:
  2705.                 \R_sync_fail$next  = \$20 [6:0];
  2706.           endcase
  2707.     endcase
  2708.     (* src = "/home/oguz286/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:519" *)
  2709.     casez (shift_rst)
  2710.       1'h1:
  2711.           \R_sync_fail$next  = 7'h00;
  2712.     endcase
  2713.   end
  2714.   assign \$1  = 5'h1f;
  2715.   assign \$6  = 5'h1f;
  2716.   assign \$11  = 5'h1f;
  2717.   assign \$20  = \$21 ;
  2718.   assign shift_rst = 1'h0;
  2719.   assign R_shift_clock_synchronizer = 8'h00;
  2720.   assign o_clk = shift_clock[1:0];
  2721.   assign o_blue = shift_blue[1:0];
  2722.   assign o_green = shift_green[1:0];
  2723.   assign o_red = shift_red[1:0];
  2724.   assign o_blue_par = latched_blue;
  2725.   assign o_green_par = latched_green;
  2726.   assign o_red_par = latched_red;
  2727.   assign encoded_blue = u23_o_encoded;
  2728.   assign u23_i_blank = i_blank;
  2729.   assign u23_i_c = c_blue;
  2730.   assign u23_i_data = blue_d;
  2731.   assign encoded_green = u22_o_encoded;
  2732.   assign u22_i_blank = i_blank;
  2733.   assign u22_i_c = 2'h0;
  2734.   assign u22_i_data = green_d;
  2735.   assign encoded_red = u21_o_encoded;
  2736.   assign u21_i_blank = i_blank;
  2737.   assign u21_i_c = 2'h0;
  2738.   assign u21_i_data = red_d;
  2739.   assign blue_d = i_blue;
  2740.   assign green_d = i_green;
  2741.   assign red_d = i_red;
  2742.   assign c_blue = { i_vsync, i_hsync };
  2743. endmodule
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