module top_kadri(
					rst_i,
					clk_i,
					kadr_i,
					hex1_o,
					hex2_o
				);

input				rst_i;
input				clk_i;
input				kadr_i;
output	reg	[6:0]	hex1_o;
output	reg	[6:0]	hex2_o;



reg	[5:0]	ch_kadr	=	0;
reg	[3:0]	dec 	=	0;
reg	[3:0]	ed 		=	0;


decoder_hex decoder_hex1 	(
								.rst	(rst_i),
								.kod	(ed),
								.hex 	(hex1_o)
							);

decoder_hex decoder_hex2 	(
								.rst	(rst_i),
								.kod	(dec),
								.hex 	(hex2_o)
							);

schet_kadrov schet_kadrov	(
								clk		(clk_i),
								rst		(rst_i),
								kadr 	(kadr_i),
								ch_kadr	(ch_kadr)
							);

always @* begin
	if (rst_i) begin
		ch_kadr <= 	6'b00_0000;
	end
	else begin
		if (ch_kadr	[5:0] > 6'b11_1100) begin //60
			dec <=	4'b0110;
			ed  <=  ch_kadr	[5:0] - 6'b11_1100;
		end else if (ch_kadr	[5:0] > 6'b11_0010) begin //50
			dec <=	4'b0101;
			ed  <=  ch_kadr	[5:0] - 6'b11_0010;
		end else if (ch_kadr	[5:0] > 6'b10_1000) begin //40
			dec <=	4'b0100;
			ed  <=  ch_kadr	[5:0] - 6'b10_1000;
		end else if (ch_kadr	[5:0] > 6'b01_1110) begin //30
			dec <=	4'b0011;
			ed  <=  ch_kadr	[5:0] - 6'b01_1110;
		end else if (ch_kadr	[5:0] > 6'b01_0100) begin //20
			dec <=	4'b0010;
			ed  <=  ch_kadr	[5:0] - 6'b01_0100;
		end else if (ch_kadr	[5:0] > 6'b00_1010) begin //10
			dec <=	4'b0001;
			ed  <=  ch_kadr	[5:0] - 6'b00_1010;
		end
	end
end

endmodule