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Mar 18th, 2018
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  1. module swfsj3(input [1:0]SW,
  2. output [1:0]LEDR);
  3. wire Q;
  4. latch_D master(SW[1], SW[0], Q);
  5. latch_D slave(~SW[1], Q, LEDR[1]);
  6.  
  7. endmodule
  8.  
  9. module latch_D(Clk, D, Q);
  10.  
  11. input Clk, D;
  12. output Q;
  13.  
  14. wire R_g, S_g, Qa, Qb /* synthesis keep */;
  15.  
  16. nand(S_g, D, Clk);
  17. nand(R_g, ~D, Clk);
  18.  
  19. nand(Qa, S_g, Qb);
  20. nand(Qb, R_g, Qa);
  21.  
  22. assign Q = Qa;
  23.  
  24. endmodule
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