--- test.v.bad	2021-06-10 22:09:26.961987347 +0200
+++ test.v	2021-06-10 22:18:48.930618984 +0200
@@ -3480,6 +3480,22 @@
     .Q(pcpi_wr_i)
   );
   (* module_not_derived = 32'd1 *)
+  (* src = "pcpi_fastmul_dsp.v:137.2-164.5|/home/tnt/data/had/fpga-toolchain.bad/bin/../share/yosys/ecp5/cells_map.v:88.171-88.230" *)
+  TRELLIS_FF #(
+    .CEMUX("INV"),
+    .CLKMUX("CLK"),
+    .GSR("DISABLED"),
+    .LSRMUX("LSR"),
+    .REGSET("RESET"),
+    .SRMODE("LSR_OVER_CE")
+  ) pcpi_wr_i_TRELLIS_FF_Q_dupe (
+    .CE(wait_stage_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_C_Z),
+    .CLK(clk),
+    .DI(pcpi_wr_i_TRELLIS_FF_Q_DI),
+    .LSR(reset),
+    .Q(pcpi_ready_i)
+  );
+  (* module_not_derived = 32'd1 *)
   (* src = "/home/tnt/data/had/fpga-toolchain.bad/bin/../share/yosys/ecp5/cells_map.v:120.33-121.56" *)
   LUT4 #(
     .INIT(16'h0f00)
@@ -8462,8 +8478,7 @@
   assign pcpi_valid_LUT4_A_Z[4:0] = { pcpi_wr_i, res_tot[0], res_tot[32], pcpi_insn[12], pcpi_insn[13] };
   assign wait_stage_TRELLIS_FF_Q_3_DI[3:2] = 2'h0;
   assign res_tot_TRELLIS_FF_Q_DI[15:0] = res_ll_ex[15:0];
-  assign pcpi_ready = pcpi_wr_i;
-  assign pcpi_ready_i = pcpi_wr_i;
+  assign pcpi_ready = pcpi_ready_i;
   assign pcpi_wait = 1'h0;
   assign pcpi_wr = pcpi_wr_i;
   assign res_hh_ex[31:0] = 32'd0;