After packing:
IOs          15 / 96
GBs          0 / 8
  GB_IOs     0 / 8
LCs          59 / 1280
  DFF        17
  CARRY      7
  CARRY, DFF 10
  DFF PASS   9
  CARRY PASS 4
BRAMs        5 / 16
WARMBOOTs    0 / 1
PLLs         0 / 1

place_constraints...
promote_globals...
  promoted clk$2, 37 / 37
  promoted $abc$22237$n78, 16 / 19
  promoted $abc$22237$n88, 11 / 11
  promoted $abc$22237$n0, 11 / 11
  promoted 4 nets
    1 sr/we
    2 cen/wclke
    1 clk
  4 globals
    1 sr/we
    2 cen/wclke
    1 clk
realize_constants...
  realized 0, 1
place...
  initial wire length = 638
  at iteration #50: temp = 5.43911, wire length = 470
  at iteration #100: temp = 2.51989, wire length = 290
  at iteration #150: temp = 0.539452, wire length = 169
  final wire length = 148

After placement:
PIOs       12 / 96
PLBs       25 / 160
BRAMs      5 / 16

  place time 0.07s
route...
  pass 1, 1 shared.
  pass 2, 0 shared.

After routing:
span_4     52 / 6944
span_12    17 / 1440

  route time 0.06s
write_txt core.asc...
icetime -d hx1k -mtr core.rpt core.asc
// Reading input .asc file..
// Reading 1k chipdb file..
// Creating timing netlist..
// Timing estimate: 8.14 ns (122.89 MHz)
icepack core.asc core.bin
[sahaj@fedora 7segcalc]$