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new libgfxinit log

andyp73
Apr 21st, 2021
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  1. SMM Module: placing jmp sequence at 0x7b007000 rel16 0x0ffd
  2. SMM Module: placing jmp sequence at 0x7b006c00 rel16 0x13fd
  3. SMM Module: placing jmp sequence at 0x7b006800 rel16 0x17fd
  4. SMM Module: placing jmp sequence at 0x7b006400 rel16 0x1bfd
  5. SMM Module: stub loaded at 0x7b008000. Will call 0x7b010c2a
  6. Clearing SMI status registers
  7. SMI_STS: PM1
  8. TMROF GPE0 STD STS: LAN_WAKE PME_B0 TCO_SCI
  9. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b000000, cpu = 0
  10. In relocation handler: CPU 0
  11. New SMBASE=0x7b000000 IEDBASE=0x7b400000
  12. Writing SMRR. base = 0x7b000006, mask=0xff800800
  13. Relocation complete.
  14. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afffc00, cpu = 1
  15. In relocation handler: CPU 1
  16. New SMBASE=0x7afffc00 IEDBASE=0x7b400000
  17. Relocation complete.
  18. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff000, cpu = 4
  19. In relocation handler: CPU 4
  20. New SMBASE=0x7afff000 IEDBASE=0x7b400000
  21. Relocation complete.
  22. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affec00, cpu = 5
  23. In relocation handler: CPU 5
  24. New SMBASE=0x7affec00 IEDBASE=0x7b400000
  25. Writing SMRR. base = 0x7b000006, mask=0xff800800
  26. Relocation complete.
  27. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe800, cpu = 6
  28. In relocation handler: CPU 6
  29. New SMBASE=0x7affe800 IEDBASE=0x7b400000
  30. Relocation complete.
  31. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe400, cpu = 7
  32. In relocation handler: CPU 7
  33. New SMBASE=0x7affe400 IEDBASE=0x7b400000
  34. Writing SMRR. base = 0x7b000006, mask=0xff800800
  35. Relocation complete.
  36. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff800, cpu = 2
  37. In relocation handler: CPU 2
  38. New SMBASE=0x7afff800 IEDBASE=0x7b400000
  39. Relocation complete.
  40. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff400, cpu = 3
  41. In relocation handler: CPU 3
  42. New SMBASE=0x7afff400 IEDBASE=0x7b400000
  43. Writing SMRR. base = 0x7b000006, mask=0xff800800
  44. Relocation complete.
  45. Initializing CPU #0
  46. CPU: vendor Intel device 806ea
  47. CPU: family 06, model 8e, stepping 0a
  48. Clearing out pending MCEs
  49. Setting up local APIC...
  50. apic_id: 0x00 done.
  51. cpu: energy policy set to 6
  52. Turbo is available but hidden
  53. Turbo is available and visible
  54. Skip microcode update
  55. CPU #0 initialized
  56. Initializing CPU #1
  57. Initializing CPU #7
  58. Initializing CPU #6
  59. CPU: vendor Intel device 806ea
  60. CPU: family 06, model 8e, stepping 0a
  61. CPU: vendor Intel device 806ea
  62. CPU: family 06, model 8e, stepping 0a
  63. Clearing out pending MCEs
  64. Clearing out pending MCEs
  65. Setting up local APIC...
  66. CPU: vendor Intel device 806ea
  67. CPU: family 06, model 8e, stepping 0a
  68. Clearing out pending MCEs
  69. Initializing CPU #5
  70. Initializing CPU #4
  71. CPU: vendor Intel device 806ea
  72. CPU: family 06, model 8e, stepping 0a
  73. CPU: vendor Intel device 806ea
  74. CPU: family 06, model 8e, stepping 0a
  75. Clearing out pending MCEs
  76. Clearing out pending MCEs
  77. Setting up local APIC...
  78. Initializing CPU #3
  79. Initializing CPU #2
  80. CPU: vendor Intel device 806ea
  81. CPU: family 06, model 8e, stepping 0a
  82. CPU: vendor Intel device 806ea
  83. CPU: family 06, model 8e, stepping 0a
  84. Clearing out pending MCEs
  85. Clearing out pending MCEs
  86. Setting up local APIC...
  87. Setting up local APIC...
  88. apic_id: 0x02 done.
  89. Setting up local APIC...
  90. Setting up local APIC...
  91. apic_id: 0x05 done.
  92. Setting up local APIC...
  93. apic_id: 0x06 done.
  94. apic_id: 0x07 done.
  95. cpu: energy policy set to 6
  96. cpu: energy policy set to 6
  97. Skip microcode update
  98. CPU #5 initialized
  99. Skip microcode update
  100. CPU #4 initialized
  101. apic_id: 0x03 done.
  102. cpu: energy policy set to 6
  103. cpu: energy policy set to 6
  104. Skip microcode update
  105. CPU #7 initialized
  106. Skip microcode update
  107. CPU #6 initialized
  108. apic_id: 0x01 done.
  109. apic_id: 0x04 done.
  110. cpu: energy policy set to 6
  111. cpu: energy policy set to 6
  112. Skip microcode update
  113. CPU #2 initialized
  114. Skip microcode update
  115. CPU #3 initialized
  116. cpu: energy policy set to 6
  117. Skip microcode update
  118. CPU #1 initialized
  119. bsp_do_flight_plan done after 472 msecs.
  120. CPU: frequency set to 4000 MHz
  121. Enabling SMIs.
  122. Locking SMM.
  123. IA32_FEATURE_CONTROL already locked; VMX status: enabled
  124. IA32_FEATURE_CONTROL already locked; VMX status: enabled
  125. IA32_FEATURE_CONTROL already locked
  126. IA32_FEATURE_CONTROL already locked; VMX status: enabled
  127. IA32_FEATURE_CONTROL already locked; VMX status: enabled
  128. IA32_FEATURE_CONTROL already locked
  129. IA32_FEATURE_CONTROL already locked
  130. IA32_FEATURE_CONTROL already locked; VMX status: enabled
  131. IA32_FEATURE_CONTROL already locked; VMX status: enabled
  132. IA32_FEATURE_CONTROL already locked
  133. IA32_FEATURE_CONTROL already locked
  134. IA32_FEATURE_CONTROL already locked; VMX status: enabled
  135. IA32_FEATURE_CONTROL already locked; VMX status: enabled
  136. IA32_FEATURE_CONTROL already locked
  137. IA32_FEATURE_CONTROL already locked
  138. BS: BS_DEV_INIT_CHIPS entry times (exec / console): 396 / 241 ms
  139. IA32_FEATURE_CONTROL already locked
  140. gpio_pad_reset_config_override: Logical to Chipset mapping not found
  141. FSPS returned 0
  142. ITSS IRQ Polarities Before:
  143. IPC0: 0x00ff4000
  144. IPC1: 0x00000007
  145. IPC2: 0x00000000
  146. IPC3: 0x00000000
  147. ITSS IRQ Polarities After:
  148. IPC0: 0x00ff4000
  149. IPC1: 0x00000007
  150. IPC2: 0x00000000
  151. IPC3: 0x00000000
  152. Found PCIe Root Port #6 at PCI: 00:1c.0.
  153. Found PCIe Root Port #9 at PCI: 00:1d.0.
  154. Remapping PCIe Root Port #6 from PCI: 00:1c.5 to new function number 0.
  155. BS: BS_DEV_INIT_CHIPS run times (exec / console): 194 / 43 ms
  156. Enumerating buses...
  157. Root Device scanning...
  158. DOMAIN: 0000 enabled
  159. CPU_CLUSTER: 0 enabled
  160. DOMAIN: 0000 scanning...
  161. PCI: pci_scan_bus for bus 00
  162. PCI: 00:00.0 [8086/5914] enabled
  163. PCI: 00:02.0 [8086/5917] enabled
  164. PCI: 00:04.0 [8086/1903] enabled
  165. PCI: 00:14.0 [8086/9d2f] enabled
  166. PCI: 00:14.2 [8086/9d31] enabled
  167. PCI: 00:15.0 [8086/9d60] enabled
  168. PCI: 00:15.1 [8086/9d61] enabled
  169. PCI: 00:15.2 [8086/9d62] disabled
  170. PCI: 00:15.3 [8086/9d63] disabled
  171. PCI: 00:17.0 [8086/9d03] enabled
  172. PCI: 00:19.0 [8086/9d66] enabled
  173. PCI: 00:19.1 [8086/9d65] disabled
  174. PCI: 00:1c.0 [8086/9d15] enabled
  175. PCI: 00:1d.0 [8086/9d18] enabled
  176. PCI: 00:1e.0 [8086/9d27] enabled
  177. PCI: 00:1e.2 [8086/9d29] disabled
  178. PCI: 00:1e.3 [8086/9d2a] disabled
  179. PCI: 00:1f.0 [8086/9d4e] enabled
  180. PCI: 00:1f.1 [8086/9d20] disabled
  181. PCI: 00:1f.2 [8086/9d21] disabled
  182. PCI: 00:1f.3 [8086/9d71] enabled
  183. PCI: 00:1f.4 [8086/9d23] enabled
  184. GPIO: 0 enabled
  185. PCI: Leftover static devices:
  186. PCI: 00:01.0
  187. PCI: 00:01.1
  188. PCI: 00:01.2
  189. PCI: 00:05.0
  190. PCI: 00:07.0
  191. PCI: 00:08.0
  192. PCI: 00:13.0
  193. PCI: 00:14.1
  194. PCI: 00:14.3
  195. PCI: 00:16.0
  196. PCI: 00:16.1
  197. PCI: 00:16.2
  198. PCI: 00:16.3
  199. PCI: 00:16.4
  200. PCI: 00:19.2
  201. PCI: 00:1b.0
  202. PCI: 00:1b.1
  203. PCI: 00:1b.2
  204. PCI: 00:1b.3
  205. PCI: 00:1b.4
  206. PCI: 00:1b.5
  207. PCI: 00:1b.6
  208. PCI: 00:1b.7
  209. PCI: 00:1d.4
  210. PCI: 00:1d.5
  211. PCI: 00:1d.6
  212. PCI: 00:1d.7
  213. PCI: 00:1e.1
  214. PCI: 00:1e.4
  215. PCI: 00:1e.5
  216. PCI: 00:1e.6
  217. PCI: 00:1f.5
  218. PCI: 00:1f.6
  219. PCI: 00:1f.7
  220. PCI: Check your devicetree.cb.
  221. PCI: 00:02.0 scanning...
  222. scan_bus: bus PCI: 00:02.0 finished in 0 msecs
  223. PCI: 00:14.0 scanning...
  224. scan_bus: bus PCI: 00:14.0 finished in 0 msecs
  225. PCI: 00:15.0 scanning...
  226. I2C: 00:2c enabled
  227. scan_bus: bus PCI: 00:15.0 finished in 1 msecs
  228. PCI: 00:15.1 scanning...
  229. scan_bus: bus PCI: 00:15.1 finished in 0 msecs
  230. PCI: 00:1c.0 scanning...
  231. PCI: pci_scan_bus for bus 01
  232. PCI: 01:00.0 [8086/24fd] enabled
  233. Enabling Common Clock Configuration
  234. L1 Sub-State supported from root port 28
  235. L1 Sub-State Support = 0xf
  236. CommonModeRestoreTime = 0x28
  237. Power On Value = 0x16, Power On Scale = 0x0
  238. ASPM: Enabled L1
  239. PCIe: Max_Payload_Size adjusted to 128
  240. PCI: 01:00.0: Enabled LTR
  241. PCI: 01:00.0: Programmed LTR max latencies
  242. scan_bus: bus PCI: 00:1c.0 finished in 37 msecs
  243. PCI: 00:1d.0 scanning...
  244. PCI: pci_scan_bus for bus 02
  245. PCI: 02:00.0 [1987/5012] enabled
  246. Enabling Common Clock Configuration
  247. PCIE CLK PM is not supported by endpoint
  248. L1 Sub-State supported from root port 29
  249. L1 Sub-State Support = 0xf
  250. CommonModeRestoreTime = 0x28
  251. Power On Value = 0x6, Power On Scale = 0x1
  252. ASPM: Enabled L1
  253. PCIe: Max_Payload_Size adjusted to 128
  254. PCI: 02:00.0: Enabled LTR
  255. PCI: 02:00.0: Programmed LTR max latencies
  256. scan_bus: bus PCI: 00:1d.0 finished in 41 msecs
  257. PCI: 00:1f.0 scanning...
  258. PNP: 004e.0 enabled
  259. scan_bus: bus PCI: 00:1f.0 finished in 2 msecs
  260. PCI: 00:1f.3 scanning...
  261. scan_bus: bus PCI: 00:1f.3 finished in 0 msecs
  262. PCI: 00:1f.4 scanning...
  263. scan_bus: bus PCI: 00:1f.4 finished in 0 msecs
  264. scan_bus: bus DOMAIN: 0000 finished in 277 msecs
  265. scan_bus: bus Root Device finished in 288 msecs
  266. done
  267. BS: BS_DEV_ENUMERATE run times (exec / console): 2 / 297 ms
  268. MRC: Could not find region 'UNIFIED_MRC_CACHE'
  269. FMAP: area RW_MRC_CACHE found @ 200000 (65536 bytes)
  270. MRC: NOT enabling PRR for 'RW_MRC_CACHE'.
  271. BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 14 ms
  272. found VGA at PCI: 00:02.0
  273. Setting up VGA for PCI: 00:02.0
  274. Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
  275. Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
  276. Allocating resources...
  277. Reading resources...
  278. Done reading resources.
  279. ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
  280. PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff
  281. PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff done
  282. PCI: 00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
  283. PCI: 01:00.0 10 * [0x0 - 0x1fff] mem
  284. PCI: 00:1c.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
  285. PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
  286. PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
  287. PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff
  288. PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff done
  289. PCI: 00:1d.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
  290. PCI: 02:00.0 10 * [0x0 - 0x3fff] mem
  291. PCI: 00:1d.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
  292. PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
  293. PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
  294. === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
  295. DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
  296. update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
  297. update_constraints: PCI: 00:1f.4 20 base 0000efa0 limit 0000efbf io (fixed)
  298. DOMAIN: 0000: Resource ranges:
  299. * Base: 1000, Size: dfa0, Tag: 100
  300. * Base: efc0, Size: 1040, Tag: 100
  301. PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
  302. PCI: 00:17.0 20 * [0x1040 - 0x105f] limit: 105f io
  303. PCI: 00:17.0 18 * [0x1060 - 0x1067] limit: 1067 io
  304. PCI: 00:17.0 1c * [0x1068 - 0x106b] limit: 106b io
  305. DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
  306. DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
  307. update_constraints: PCI: 00:00.0 00 base e0000000 limit efffffff mem (fixed)
  308. update_constraints: PCI: 00:00.0 01 base fed10000 limit fed17fff mem (fixed)
  309. update_constraints: PCI: 00:00.0 02 base fed18000 limit fed18fff mem (fixed)
  310. update_constraints: PCI: 00:00.0 03 base fed19000 limit fed19fff mem (fixed)
  311. update_constraints: PCI: 00:00.0 04 base fed84000 limit fed84fff mem (fixed)
  312. update_constraints: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed)
  313. update_constraints: PCI: 00:00.0 06 base fed90000 limit fed90fff mem (fixed)
  314. update_constraints: PCI: 00:00.0 07 base fed91000 limit fed91fff mem (fixed)
  315. update_constraints: PCI: 00:00.0 08 base 00000000 limit 0009ffff mem (fixed)
  316. update_constraints: PCI: 00:00.0 09 base 000c0000 limit 7affffff mem (fixed)
  317. update_constraints: PCI: 00:00.0 0a base 7b000000 limit 7fffffff mem (fixed)
  318. update_constraints: PCI: 00:00.0 0b base 100000000 limit 27fffffff mem (fixed)
  319. update_constraints: PCI: 00:00.0 0c base 000a0000 limit 000bffff mem (fixed)
  320. update_constraints: PCI: 00:00.0 0d base 000c0000 limit 000fffff mem (fixed)
  321. update_constraints: PCI: 00:19.0 10 base fe030000 limit fe030fff mem (fixed)
  322. DOMAIN: 0000: Resource ranges:
  323. * Base: 80000000, Size: 60000000, Tag: 200
  324. * Base: f0000000, Size: e030000, Tag: 200
  325. * Base: fe031000, Size: cdf000, Tag: 200
  326. * Base: fed1a000, Size: 66000, Tag: 200
  327. * Base: fed85000, Size: b000, Tag: 200
  328. * Base: fed92000, Size: 126e000, Tag: 200
  329. * Base: 280000000, Size: 7d80000000, Tag: 100200
  330. PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
  331. PCI: 00:02.0 10 * [0x90000000 - 0x90ffffff] limit: 90ffffff mem
  332. PCI: 00:1c.0 20 * [0x91000000 - 0x910fffff] limit: 910fffff mem
  333. PCI: 00:1d.0 20 * [0x91100000 - 0x911fffff] limit: 911fffff mem
  334. PCI: 00:14.0 10 * [0x91200000 - 0x9120ffff] limit: 9120ffff mem
  335. PCI: 00:1f.3 20 * [0x91210000 - 0x9121ffff] limit: 9121ffff mem
  336. PCI: 00:04.0 10 * [0x91220000 - 0x91227fff] limit: 91227fff mem
  337. PCI: 00:1f.3 10 * [0x91228000 - 0x9122bfff] limit: 9122bfff mem
  338. PCI: 00:17.0 10 * [0x9122c000 - 0x9122dfff] limit: 9122dfff mem
  339. PCI: 00:14.2 10 * [0x9122e000 - 0x9122efff] limit: 9122efff mem
  340. PCI: 00:15.0 10 * [0x9122f000 - 0x9122ffff] limit: 9122ffff mem
  341. PCI: 00:15.1 10 * [0x91230000 - 0x91230fff] limit: 91230fff mem
  342. PCI: 00:19.0 18 * [0x91231000 - 0x91231fff] limit: 91231fff mem
  343. PCI: 00:1e.0 10 * [0x91232000 - 0x91232fff] limit: 91232fff mem
  344. PCI: 00:1e.0 18 * [0x91233000 - 0x91233fff] limit: 91233fff mem
  345. PCI: 00:17.0 24 * [0x91234000 - 0x912347ff] limit: 912347ff mem
  346. PCI: 00:17.0 14 * [0x91235000 - 0x912350ff] limit: 912350ff mem
  347. PCI: 00:1f.4 10 * [0x91236000 - 0x912360ff] limit: 912360ff mem
  348. DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
  349. PCI: 00:1c.0 mem: base: 91000000 size: 100000 align: 20 gran: 20 limit: 910fffff
  350. PCI: 00:1c.0: Resource ranges:
  351. * Base: 91000000, Size: 100000, Tag: 200
  352. PCI: 01:00.0 10 * [0x91000000 - 0x91001fff] limit: 91001fff mem
  353. PCI: 00:1c.0 mem: base: 91000000 size: 100000 align: 20 gran: 20 limit: 910fffff done
  354. PCI: 00:1d.0 mem: base: 91100000 size: 100000 align: 20 gran: 20 limit: 911fffff
  355. PCI: 00:1d.0: Resource ranges:
  356. * Base: 91100000, Size: 100000, Tag: 200
  357. PCI: 02:00.0 10 * [0x91100000 - 0x91103fff] limit: 91103fff mem
  358. PCI: 00:1d.0 mem: base: 91100000 size: 100000 align: 20 gran: 20 limit: 911fffff done
  359. === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
  360. PCI: 00:02.0 10 <- [0x0090000000 - 0x0090ffffff] size 0x01000000 gran 0x18 mem64
  361. PCI: 00:02.0 18 <- [0x0080000000 - 0x008fffffff] size 0x10000000 gran 0x1c prefmem64
  362. PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
  363. PCI: 00:04.0 10 <- [0x0091220000 - 0x0091227fff] size 0x00008000 gran 0x0f mem64
  364. PCI: 00:14.0 10 <- [0x0091200000 - 0x009120ffff] size 0x00010000 gran 0x10 mem64
  365. PCI: 00:14.2 10 <- [0x009122e000 - 0x009122efff] size 0x00001000 gran 0x0c mem64
  366. PCI: 00:15.0 10 <- [0x009122f000 - 0x009122ffff] size 0x00001000 gran 0x0c mem64
  367. PCI: 00:15.1 10 <- [0x0091230000 - 0x0091230fff] size 0x00001000 gran 0x0c mem64
  368. PCI: 00:17.0 10 <- [0x009122c000 - 0x009122dfff] size 0x00002000 gran 0x0d mem
  369. PCI: 00:17.0 14 <- [0x0091235000 - 0x00912350ff] size 0x00000100 gran 0x08 mem
  370. PCI: 00:17.0 18 <- [0x0000001060 - 0x0000001067] size 0x00000008 gran 0x03 io
  371. PCI: 00:17.0 1c <- [0x0000001068 - 0x000000106b] size 0x00000004 gran 0x02 io
  372. PCI: 00:17.0 20 <- [0x0000001040 - 0x000000105f] size 0x00000020 gran 0x05 io
  373. PCI: 00:17.0 24 <- [0x0091234000 - 0x00912347ff] size 0x00000800 gran 0x0b mem
  374. PCI: 00:19.0 18 <- [0x0091231000 - 0x0091231fff] size 0x00001000 gran 0x0c mem64
  375. PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
  376. PCI: 00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
  377. PCI: 00:1c.0 20 <- [0x0091000000 - 0x00910fffff] size 0x00100000 gran 0x14 bus 01 mem
  378. PCI: 01:00.0 10 <- [0x0091000000 - 0x0091001fff] size 0x00002000 gran 0x0d mem64
  379. PCI: 00:1d.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
  380. PCI: 00:1d.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 02 prefmem
  381. PCI: 00:1d.0 20 <- [0x0091100000 - 0x00911fffff] size 0x00100000 gran 0x14 bus 02 mem
  382. PCI: 02:00.0 10 <- [0x0091100000 - 0x0091103fff] size 0x00004000 gran 0x0e mem64
  383. PCI: 00:1e.0 10 <- [0x0091232000 - 0x0091232fff] size 0x00001000 gran 0x0c mem64
  384. PCI: 00:1e.0 18 <- [0x0091233000 - 0x0091233fff] size 0x00001000 gran 0x0c mem64
  385. PCI: 00:1f.3 10 <- [0x0091228000 - 0x009122bfff] size 0x00004000 gran 0x0e mem64
  386. PCI: 00:1f.3 20 <- [0x0091210000 - 0x009121ffff] size 0x00010000 gran 0x10 mem64
  387. PCI: 00:1f.4 10 <- [0x0091236000 - 0x00912360ff] size 0x00000100 gran 0x08 mem64
  388. Done setting resources.
  389. Done allocating resources.
  390. BS: BS_DEV_RESOURCES run times (exec / console): 3 / 765 ms
  391. Enabling resources...
  392. PCI: 00:00.0 subsystem <- 8086/5914
  393. PCI: 00:00.0 cmd <- 06
  394. PCI: 00:02.0 subsystem <- 8086/5917
  395. PCI: 00:02.0 cmd <- 03
  396. PCI: 00:04.0 subsystem <- 8086/1903
  397. PCI: 00:04.0 cmd <- 02
  398. PCI: 00:14.0 subsystem <- 8086/9d2f
  399. PCI: 00:14.0 cmd <- 02
  400. PCI: 00:14.2 subsystem <- 8086/9d31
  401. PCI: 00:14.2 cmd <- 02
  402. PCI: 00:15.0 subsystem <- 8086/9d60
  403. PCI: 00:15.0 cmd <- 06
  404. PCI: 00:15.1 subsystem <- 8086/9d61
  405. PCI: 00:15.1 cmd <- 06
  406. PCI: 00:17.0 subsystem <- 8086/9d03
  407. PCI: 00:17.0 cmd <- 03
  408. PCI: 00:19.0 subsystem <- 8086/9d66
  409. PCI: 00:19.0 cmd <- 06
  410. PCI: 00:1c.0 bridge ctrl <- 0013
  411. PCI: 00:1c.0 subsystem <- 8086/9d15
  412. PCI: 00:1c.0 cmd <- 06
  413. PCI: 00:1d.0 bridge ctrl <- 0013
  414. PCI: 00:1d.0 subsystem <- 8086/9d18
  415. PCI: 00:1d.0 cmd <- 06
  416. PCI: 00:1e.0 subsystem <- 8086/9d27
  417. PCI: 00:1e.0 cmd <- 02
  418. PCI: 00:1f.0 subsystem <- 8086/9d4e
  419. PCI: 00:1f.0 cmd <- 07
  420. PCI: 00:1f.3 subsystem <- 8086/9d71
  421. PCI: 00:1f.3 cmd <- 02
  422. PCI: 00:1f.4 subsystem <- 8086/9d23
  423. PCI: 00:1f.4 cmd <- 03
  424. PCI: 01:00.0 subsystem <- 8086/24fd
  425. PCI: 01:00.0 cmd <- 02
  426. PCI: 02:00.0 subsystem <- 1987/5012
  427. PCI: 02:00.0 cmd <- 02
  428. done.
  429. BS: BS_DEV_ENABLE run times (exec / console): 1 / 110 ms
  430. HECI: No CSE device
  431. BS: BS_DEV_ENABLE exit times (exec / console): 0 / 2 ms
  432. Initializing devices...
  433. PCI: 00:00.0 init
  434. CPU TDP = 15 Watts
  435. CPU PL1 = 20 Watts
  436. CPU PL2 = 30 Watts
  437. PCI: 00:00.0 init finished in 6 msecs
  438. PCI: 00:02.0 init
  439. CBFS: Found 'vbt.bin' @0x99640 size 0x4a4 in mcache @0x7abfd214
  440. Found a VBT of 6144 bytes after decompression
  441. GMA: Found VBT in CBFS
  442. GMA: Found valid VBT in CBFS
  443. [2.170883] HW.GFX.GMA.Initialize
  444. [2.173985] HW.GFX.GMA.Panel.Setup_PP_Sequencer
  445. [2.178626] HW.GFX.GMA.Panel.Setup_PP_Sequencer
  446. [2.183276] HW.GFX.GMA.Registers.Read: 0x07d001f4 <- 0x000c7208:PCH_PP_ON_DELAYS
  447. [2.191205] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c720c:PCH_PP_OFF_DELAYS
  448. [2.199230] HW.GFX.GMA.Registers.Read: 0x0004af06 <- 0x000c7210:PCH_PP_DIVISOR
  449. [2.206956] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_ON_DELAYS
  450. [2.213735] HW.GFX.GMA.Registers.Read: 0x07d001f4 <- 0x000c7208:PCH_PP_ON_DELAYS
  451. [2.221654] HW.GFX.GMA.Registers.Write: 0x07d00001 -> 0x000c7208:PCH_PP_ON_DELAYS
  452. [2.229595] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_OFF_DELAYS
  453. [2.236459] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c720c:PCH_PP_OFF_DELAYS
  454. [2.244476] HW.GFX.GMA.Registers.Write: 0x138801f4 -> 0x000c720c:PCH_PP_OFF_DELAYS
  455. [2.252512] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_DIVISOR
  456. [2.259088] HW.GFX.GMA.Registers.Read: 0x0004af06 <- 0x000c7210:PCH_PP_DIVISOR
  457. [2.266813] HW.GFX.GMA.Registers.Write: 0x0004af06 -> 0x000c7210:PCH_PP_DIVISOR
  458. [2.274559] HW.GFX.GMA.Registers.Set_Mask: 0x00000002 .S PCH_PP_CONTROL
  459. [2.281522] HW.GFX.GMA.Registers.Read: 0x00000008 <- 0x000c7204:PCH_PP_CONTROL
  460. [2.289249] HW.GFX.GMA.Registers.Write: 0x0000000a -> 0x000c7204:PCH_PP_CONTROL
  461. [2.296994] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  462. [2.302787] HW.GFX.GMA.Registers.Read: 0x00000091 <- 0x00064000:DDI_BUF_CTL_A
  463. [2.310426] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL
  464. [2.316819] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c4030:SHOTPLUG_CTL
  465. [2.324352] HW.GFX.GMA.Registers.Write: 0x13000000 -> 0x000c4030:SHOTPLUG_CTL
  466. [2.331906] HW.GFX.GMA.Registers.Is_Set_Mask: SFUSE_STRAP
  467. [2.337516] HW.GFX.GMA.Registers.Read: 0x00000006 <- 0x000c2014:SFUSE_STRAP
  468. [2.344953] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL
  469. [2.351345] HW.GFX.GMA.Registers.Read: 0x10000000 <- 0x000c4030:SHOTPLUG_CTL
  470. [2.358877] HW.GFX.GMA.Registers.Write: 0x10000013 -> 0x000c4030:SHOTPLUG_CTL
  471. [2.366430] HW.GFX.GMA.Registers.Is_Set_Mask: SFUSE_STRAP
  472. [2.372040] HW.GFX.GMA.Registers.Read: 0x00000006 <- 0x000c2014:SFUSE_STRAP
  473. [2.379478] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL
  474. [2.385869] HW.GFX.GMA.Registers.Read: 0x10000010 <- 0x000c4030:SHOTPLUG_CTL
  475. [2.393404] HW.GFX.GMA.Registers.Write: 0x10001310 -> 0x000c4030:SHOTPLUG_CTL
  476. [2.400958] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064e00:DDI_BUF_TRANS_A_S0T1
  477. [2.409267] HW.GFX.GMA.Registers.Write: 0x000000a1 -> 0x00064e04:DDI_BUF_TRANS_A_S0T2
  478. [2.417584] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064e08:DDI_BUF_TRANS_A_S1T1
  479. [2.425902] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064e0c:DDI_BUF_TRANS_A_S1T2
  480. [2.434221] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064e10:DDI_BUF_TRANS_A_S2T1
  481. [2.442538] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064e14:DDI_BUF_TRANS_A_S2T2
  482. [2.450858] HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064e18:DDI_BUF_TRANS_A_S3T1
  483. [2.459174] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e1c:DDI_BUF_TRANS_A_S3T2
  484. [2.467492] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064e20:DDI_BUF_TRANS_A_S4T1
  485. [2.475809] HW.GFX.GMA.Registers.Write: 0x0000009d -> 0x00064e24:DDI_BUF_TRANS_A_S4T2
  486. [2.484126] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064e28:DDI_BUF_TRANS_A_S5T1
  487. [2.492444] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e2c:DDI_BUF_TRANS_A_S5T2
  488. [2.500761] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064e30:DDI_BUF_TRANS_A_S6T1
  489. [2.509079] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e34:DDI_BUF_TRANS_A_S6T2
  490. [2.517397] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064e38:DDI_BUF_TRANS_A_S7T1
  491. [2.525713] HW.GFX.GMA.Registers.Write: 0x0000004f -> 0x00064e3c:DDI_BUF_TRANS_A_S7T2
  492. [2.534031] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064e40:DDI_BUF_TRANS_A_S8T1
  493. [2.542350] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e44:DDI_BUF_TRANS_A_S8T2
  494. [2.550669] HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064e48:DDI_BUF_TRANS_A_S9T1
  495. [2.558986] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064e4c:DDI_BUF_TRANS_A_S9T2
  496. [2.567305] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064e60:DDI_BUF_TRANS_B_S0T1
  497. [2.575622] HW.GFX.GMA.Registers.Write: 0x000000a1 -> 0x00064e64:DDI_BUF_TRANS_B_S0T2
  498. [2.583941] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064e68:DDI_BUF_TRANS_B_S1T1
  499. [2.592260] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064e6c:DDI_BUF_TRANS_B_S1T2
  500. [2.600578] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064e70:DDI_BUF_TRANS_B_S2T1
  501. [2.608897] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064e74:DDI_BUF_TRANS_B_S2T2
  502. [2.617216] HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064e78:DDI_BUF_TRANS_B_S3T1
  503. [2.625536] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e7c:DDI_BUF_TRANS_B_S3T2
  504. [2.633854] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064e80:DDI_BUF_TRANS_B_S4T1
  505. [2.642173] HW.GFX.GMA.Registers.Write: 0x0000009d -> 0x00064e84:DDI_BUF_TRANS_B_S4T2
  506. [2.650491] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064e88:DDI_BUF_TRANS_B_S5T1
  507. [2.658810] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e8c:DDI_BUF_TRANS_B_S5T2
  508. [2.667129] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064e90:DDI_BUF_TRANS_B_S6T1
  509. [2.675448] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e94:DDI_BUF_TRANS_B_S6T2
  510. [2.683766] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064e98:DDI_BUF_TRANS_B_S7T1
  511. [2.692083] HW.GFX.GMA.Registers.Write: 0x0000004f -> 0x00064e9c:DDI_BUF_TRANS_B_S7T2
  512. [2.700403] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064ea0:DDI_BUF_TRANS_B_S8T1
  513. [2.708722] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064ea4:DDI_BUF_TRANS_B_S8T2
  514. [2.717042] HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064ea8:DDI_BUF_TRANS_B_S9T1
  515. [2.725360] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064eac:DDI_BUF_TRANS_B_S9T2
  516. [2.733678] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064ec0:DDI_BUF_TRANS_C_S0T1
  517. [2.741996] HW.GFX.GMA.Registers.Write: 0x000000a1 -> 0x00064ec4:DDI_BUF_TRANS_C_S0T2
  518. [2.750316] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064ec8:DDI_BUF_TRANS_C_S1T1
  519. [2.758634] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064ecc:DDI_BUF_TRANS_C_S1T2
  520. [2.766953] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064ed0:DDI_BUF_TRANS_C_S2T1
  521. [2.775271] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064ed4:DDI_BUF_TRANS_C_S2T2
  522. [2.783590] HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064ed8:DDI_BUF_TRANS_C_S3T1
  523. [2.791908] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064edc:DDI_BUF_TRANS_C_S3T2
  524. [2.800227] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064ee0:DDI_BUF_TRANS_C_S4T1
  525. [2.808546] HW.GFX.GMA.Registers.Write: 0x0000009d -> 0x00064ee4:DDI_BUF_TRANS_C_S4T2
  526. [2.816864] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064ee8:DDI_BUF_TRANS_C_S5T1
  527. [2.825183] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064eec:DDI_BUF_TRANS_C_S5T2
  528. [2.833503] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064ef0:DDI_BUF_TRANS_C_S6T1
  529. [2.841821] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064ef4:DDI_BUF_TRANS_C_S6T2
  530. [2.850138] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064ef8:DDI_BUF_TRANS_C_S7T1
  531. [2.858458] HW.GFX.GMA.Registers.Write: 0x0000004f -> 0x00064efc:DDI_BUF_TRANS_C_S7T2
  532. [2.866778] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064f00:DDI_BUF_TRANS_C_S8T1
  533. [2.875096] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064f04:DDI_BUF_TRANS_C_S8T2
  534. [2.883416] HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064f08:DDI_BUF_TRANS_C_S9T1
  535. [2.891734] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064f0c:DDI_BUF_TRANS_C_S9T2
  536. [2.900054] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DISPIO_CR_TX_BMU_CR0
  537. [2.907211] HW.GFX.GMA.Registers.Read: 0x08865800 <- 0x0006c00c:DISPIO_CR_TX_BMU_CR0
  538. [2.915530] HW.GFX.GMA.Registers.Write: 0x0036db00 -> 0x0006c00c:DISPIO_CR_TX_BMU_CR0
  539. [2.923949] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S CPU_VGACNTRL
  540. [2.930570] HW.GFX.GMA.Registers.Read: 0x80002900 <- 0x00041000:CPU_VGACNTRL
  541. [2.938113] HW.GFX.GMA.Registers.Write: 0x80002900 -> 0x00041000:CPU_VGACNTRL
  542. [2.945657] HW.GFX.GMA.Registers.Set_Mask: 0x000f8000 .S DPLL_CTRL2
  543. [2.952233] HW.GFX.GMA.Registers.Read: 0x00ad00c1 <- 0x0006c05c:DPLL_CTRL2
  544. [2.959584] HW.GFX.GMA.Registers.Write: 0x00af80c1 -> 0x0006c05c:DPLL_CTRL2
  545. [2.966937] HW.GFX.GMA.Registers.Set_Mask: 0x00000010 .S NDE_RSTWRN_OPT
  546. [2.973901] HW.GFX.GMA.Registers.Read: 0x00000030 <- 0x00046408:NDE_RSTWRN_OPT
  547. [2.981640] HW.GFX.GMA.Registers.Write: 0x00000030 -> 0x00046408:NDE_RSTWRN_OPT
  548. [2.989379] HW.GFX.GMA.Registers.Wait: 0x08000000 <- 0x08000000 & 0x00042000:FUSE_STATUS
  549. [2.998086] HW.GFX.GMA.Power_And_Clocks.PD_On
  550. [3.002534] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS
  551. [3.010562] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x00045404:PWR_WELL_CTL_DRIVER
  552. [3.018786] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  553. [3.026814] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  554. [3.034941] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  555. [3.042585] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  556. [3.050227] HW.GFX.GMA.Registers.Set_Mask: 0x20000000 .S PWR_WELL_CTL_DRIVER
  557. [3.057676] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x00045404:PWR_WELL_CTL_DRIVER
  558. [3.065898] HW.GFX.GMA.Registers.Write: 0x70000001 -> 0x00045404:PWR_WELL_CTL_DRIVER
  559. [3.074121] HW.GFX.GMA.Registers.Wait: 0x10000000 <- 0x10000000 & 0x00045404:PWR_WELL_CTL_DRIVER
  560. [3.083602] HW.GFX.GMA.Registers.Wait: 0x04000000 <- 0x04000000 & 0x00042000:FUSE_STATUS
  561. [3.092307] HW.GFX.GMA.Power_And_Clocks.PD_On
  562. [3.096758] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS
  563. [3.104788] HW.GFX.GMA.Registers.Read: 0x70000001 <- 0x00045404:PWR_WELL_CTL_DRIVER
  564. [3.113010] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  565. [3.121040] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  566. [3.129166] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  567. [3.136808] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  568. [3.144450] HW.GFX.GMA.Registers.Set_Mask: 0x00000002 .S PWR_WELL_CTL_DRIVER
  569. [3.151900] HW.GFX.GMA.Registers.Read: 0x70000001 <- 0x00045404:PWR_WELL_CTL_DRIVER
  570. [3.160122] HW.GFX.GMA.Registers.Write: 0x70000003 -> 0x00045404:PWR_WELL_CTL_DRIVER
  571. [3.168346] HW.GFX.GMA.Registers.Wait: 0x00000001 <- 0x00000001 & 0x00045404:PWR_WELL_CTL_DRIVER
  572. [3.177826] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S LCPLL1_CTL
  573. [3.184406] HW.GFX.GMA.Registers.Read: 0xc0000000 <- 0x00046010:LCPLL1_CTL
  574. [3.191757] HW.GFX.GMA.Registers.Write: 0xc0000000 -> 0x00046010:LCPLL1_CTL
  575. [3.199108] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00046010:LCPLL1_CTL
  576. [3.207717] HW.GFX.GMA.Registers.Read: 0x0c000544 <- 0x00046000:CDCLK_CTL
  577. [3.214971] HW.GFX.GMA.Registers.Read: 0x20400042 <- 0x00051000:DFSM
  578. [3.221742] HW.GFX.GMA.PCode.Mailbox_Write_Read
  579. [3.226384] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
  580. [3.234995] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA
  581. [3.242829] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1
  582. [3.250859] HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX
  583. [3.258211] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
  584. [3.266823] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA
  585. [3.274657] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x0013812c:GT_MAILBOX_DATA_1
  586. [3.282686] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00138128:GT_MAILBOX_DATA
  587. [3.290522] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1
  588. [3.298552] HW.GFX.GMA.PCode.Mailbox_Write_Read
  589. [3.303195] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA
  590. [3.311031] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1
  591. [3.319061] HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX
  592. [3.326414] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
  593. [3.335025] HW.GFX.GMA.Registers.Read: 0x00000001 <- 0x00138128:GT_MAILBOX_DATA
  594. [3.342858] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x0013812c:GT_MAILBOX_DATA_1
  595. [3.350888] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00138128:GT_MAILBOX_DATA
  596. [3.358725] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1
  597. [3.366753] HW.GFX.GMA.Registers.Write: 0x080002a1 -> 0x00046000:CDCLK_CTL
  598. [3.374009] HW.GFX.GMA.PCode.Mailbox_Write_Read
  599. [3.378652] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00138128:GT_MAILBOX_DATA
  600. [3.386488] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1
  601. [3.394516] HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX
  602. [3.401869] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S DBUF_CTL
  603. [3.408253] HW.GFX.GMA.Registers.Read: 0x0000000a <- 0x00045008:DBUF_CTL
  604. [3.415412] HW.GFX.GMA.Registers.Write: 0x8000000a -> 0x00045008:DBUF_CTL
  605. [3.422573] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045008:DBUF_CTL
  606. [3.430988] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_RAWCLK_FREQ
  607. [3.437672] HW.GFX.GMA.Registers.Read: 0x00000018 <- 0x000c6204:PCH_RAWCLK_FREQ
  608. [3.445498] HW.GFX.GMA.Registers.Write: 0x00000018 -> 0x000c6204:PCH_RAWCLK_FREQ
  609. [3.453346] HW.GFX.GMA.Panel.On
  610. [3.456431] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_PP_CONTROL
  611. [3.462341] HW.GFX.GMA.Registers.Read: 0x0000000a <- 0x000c7204:PCH_PP_CONTROL
  612. [3.470071] HW.GFX.GMA.Registers.Set_Mask: 0x00000001 .S PCH_PP_CONTROL
  613. [3.477046] HW.GFX.GMA.Registers.Read: 0x0000000a <- 0x000c7204:PCH_PP_CONTROL
  614. [3.484777] HW.GFX.GMA.Registers.Write: 0x0000000b -> 0x000c7204:PCH_PP_CONTROL
  615. [3.492523] HW.GFX.GMA.Panel.Wait_On
  616. [3.692524] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x30000000 & 0x000c7200:PCH_PP_STATUS
  617. [3.701250] HW.GFX.GMA.Registers.Unset_Mask: 0x00000008 !S PCH_PP_CONTROL
  618. [3.708406] HW.GFX.GMA.Registers.Read: 0x0000000b <- 0x000c7204:PCH_PP_CONTROL
  619. [3.716137] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x000c7204:PCH_PP_CONTROL
  620. [3.723886] HW.GFX.GMA.Display_Probing.Read_EDID
  621. [3.728616] HW.GFX.GMA.Power_And_Clocks.PD_On
  622. [3.733065] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS
  623. [3.741092] HW.GFX.GMA.Registers.Read: 0x70000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
  624. [3.749313] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  625. [3.757342] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  626. [3.765465] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  627. [3.773106] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  628. [3.780748] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER
  629. [3.790225] HW.GFX.GMA.Registers.Set_Mask: 0x00000008 .S PWR_WELL_CTL_DRIVER
  630. [3.797673] HW.GFX.GMA.Registers.Read: 0x70000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
  631. [3.805897] HW.GFX.GMA.Registers.Write: 0x7000000b -> 0x00045404:PWR_WELL_CTL_DRIVER
  632. [3.814119] HW.GFX.GMA.Registers.Wait: 0x00000004 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER
  633. [3.823599] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  634. [3.829403] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064010:DDI_AUX_CTL_A
  635. [3.837043] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064014:DDI_AUX_DATA_A_1
  636. [3.844974] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  637. [3.851455] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064010:DDI_AUX_CTL_A
  638. [3.859097] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064010:DDI_AUX_CTL_A
  639. [3.866738] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  640. [3.875636] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  641. [3.883274] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  642. [3.891203] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  643. [3.897005] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  644. [3.904645] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064014:DDI_AUX_DATA_A_1
  645. [3.912576] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00064018:DDI_AUX_DATA_A_2
  646. [3.920505] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  647. [3.926983] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  648. [3.934623] HW.GFX.GMA.Registers.Write: 0xd650023f -> 0x00064010:DDI_AUX_CTL_A
  649. [3.942263] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  650. [3.951162] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  651. [3.958801] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  652. [3.966731] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  653. [3.972533] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  654. [3.980172] HW.GFX.GMA.Registers.Write: 0x00005000 -> 0x00064014:DDI_AUX_DATA_A_1
  655. [3.988103] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  656. [3.994582] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  657. [4.002221] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064010:DDI_AUX_CTL_A
  658. [4.009862] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  659. [4.018762] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  660. [4.026400] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  661. [4.034329] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  662. [4.040129] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  663. [4.047769] HW.GFX.GMA.Registers.Write: 0x50005000 -> 0x00064014:DDI_AUX_DATA_A_1
  664. [4.055700] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  665. [4.062178] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  666. [4.069816] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064010:DDI_AUX_CTL_A
  667. [4.077455] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  668. [4.086353] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  669. [4.093992] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  670. [4.101922] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  671. [4.107723] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  672. [4.115361] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  673. [4.123291] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  674. [4.129771] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  675. [4.137410] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  676. [4.145050] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  677. [4.153948] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  678. [4.161586] HW.GFX.GMA.Registers.Read: 0x0000ffff <- 0x00064014:DDI_AUX_DATA_A_1
  679. [4.169516] HW.GFX.GMA.Registers.Read: 0xffffffff <- 0x00064018:DDI_AUX_DATA_A_2
  680. [4.177445] HW.GFX.GMA.Registers.Read: 0x004d1025 <- 0x0006401c:DDI_AUX_DATA_A_3
  681. [4.185375] HW.GFX.GMA.Registers.Read: 0x14000000 <- 0x00064020:DDI_AUX_DATA_A_4
  682. [4.193305] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064024:DDI_AUX_DATA_A_5
  683. [4.201234] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  684. [4.207037] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  685. [4.214678] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  686. [4.222608] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  687. [4.229087] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  688. [4.236726] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  689. [4.244365] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  690. [4.253262] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  691. [4.260900] HW.GFX.GMA.Registers.Read: 0x000d1801 <- 0x00064014:DDI_AUX_DATA_A_1
  692. [4.268830] HW.GFX.GMA.Registers.Read: 0x04a51d11 <- 0x00064018:DDI_AUX_DATA_A_2
  693. [4.276762] HW.GFX.GMA.Registers.Read: 0x7806de50 <- 0x0006401c:DDI_AUX_DATA_A_3
  694. [4.284691] HW.GFX.GMA.Registers.Read: 0xa3544c99 <- 0x00064020:DDI_AUX_DATA_A_4
  695. [4.292622] HW.GFX.GMA.Registers.Read: 0x26000000 <- 0x00064024:DDI_AUX_DATA_A_5
  696. [4.300549] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  697. [4.306353] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  698. [4.313990] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  699. [4.321920] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  700. [4.328401] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  701. [4.336040] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  702. [4.343683] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  703. [4.352579] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  704. [4.360216] HW.GFX.GMA.Registers.Read: 0x000f5054 <- 0x00064014:DDI_AUX_DATA_A_1
  705. [4.368146] HW.GFX.GMA.Registers.Read: 0x00000001 <- 0x00064018:DDI_AUX_DATA_A_2
  706. [4.376073] HW.GFX.GMA.Registers.Read: 0x01010101 <- 0x0006401c:DDI_AUX_DATA_A_3
  707. [4.384005] HW.GFX.GMA.Registers.Read: 0x01010101 <- 0x00064020:DDI_AUX_DATA_A_4
  708. [4.391933] HW.GFX.GMA.Registers.Read: 0x01000000 <- 0x00064024:DDI_AUX_DATA_A_5
  709. [4.399864] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  710. [4.405667] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  711. [4.413304] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  712. [4.421234] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  713. [4.427712] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  714. [4.435352] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  715. [4.442991] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  716. [4.451889] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  717. [4.459528] HW.GFX.GMA.Registers.Read: 0x00010101 <- 0x00064014:DDI_AUX_DATA_A_1
  718. [4.467455] HW.GFX.GMA.Registers.Read: 0x0101011a <- 0x00064018:DDI_AUX_DATA_A_2
  719. [4.475385] HW.GFX.GMA.Registers.Read: 0x3680a070 <- 0x0006401c:DDI_AUX_DATA_A_3
  720. [4.483314] HW.GFX.GMA.Registers.Read: 0x381f4030 <- 0x00064020:DDI_AUX_DATA_A_4
  721. [4.491241] HW.GFX.GMA.Registers.Read: 0x20000000 <- 0x00064024:DDI_AUX_DATA_A_5
  722. [4.499171] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  723. [4.504973] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  724. [4.512611] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  725. [4.520540] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  726. [4.527017] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  727. [4.534657] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  728. [4.542294] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  729. [4.551192] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  730. [4.558832] HW.GFX.GMA.Registers.Read: 0x00350026 <- 0x00064014:DDI_AUX_DATA_A_1
  731. [4.566759] HW.GFX.GMA.Registers.Read: 0xa5100000 <- 0x00064018:DDI_AUX_DATA_A_2
  732. [4.574688] HW.GFX.GMA.Registers.Read: 0x18542b80 <- 0x0006401c:DDI_AUX_DATA_A_3
  733. [4.582616] HW.GFX.GMA.Registers.Read: 0xa070381f <- 0x00064020:DDI_AUX_DATA_A_4
  734. [4.590544] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00064024:DDI_AUX_DATA_A_5
  735. [4.598472] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  736. [4.604274] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  737. [4.611913] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  738. [4.619841] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  739. [4.626319] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  740. [4.633958] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  741. [4.641596] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  742. [4.650492] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  743. [4.658128] HW.GFX.GMA.Registers.Read: 0x00302035 <- 0x00064014:DDI_AUX_DATA_A_1
  744. [4.666059] HW.GFX.GMA.Registers.Read: 0x0026a510 <- 0x00064018:DDI_AUX_DATA_A_2
  745. [4.673988] HW.GFX.GMA.Registers.Read: 0x00001800 <- 0x0006401c:DDI_AUX_DATA_A_3
  746. [4.681916] HW.GFX.GMA.Registers.Read: 0x00001000 <- 0x00064020:DDI_AUX_DATA_A_4
  747. [4.689846] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064024:DDI_AUX_DATA_A_5
  748. [4.697775] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  749. [4.703575] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  750. [4.711213] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  751. [4.719141] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  752. [4.725620] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  753. [4.733256] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  754. [4.740896] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  755. [4.749792] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  756. [4.757427] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  757. [4.765357] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064018:DDI_AUX_DATA_A_2
  758. [4.773285] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x0006401c:DDI_AUX_DATA_A_3
  759. [4.781213] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064020:DDI_AUX_DATA_A_4
  760. [4.789141] HW.GFX.GMA.Registers.Read: 0xfc000000 <- 0x00064024:DDI_AUX_DATA_A_5
  761. [4.797070] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  762. [4.802872] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  763. [4.810510] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  764. [4.818439] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  765. [4.824916] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  766. [4.832554] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  767. [4.840194] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  768. [4.849090] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  769. [4.856727] HW.GFX.GMA.Registers.Read: 0x00004c51 <- 0x00064014:DDI_AUX_DATA_A_1
  770. [4.864656] HW.GFX.GMA.Registers.Read: 0x3133334d <- 0x00064018:DDI_AUX_DATA_A_2
  771. [4.872584] HW.GFX.GMA.Registers.Read: 0x314a5730 <- 0x0006401c:DDI_AUX_DATA_A_3
  772. [4.880513] HW.GFX.GMA.Registers.Read: 0x380a2000 <- 0x00064020:DDI_AUX_DATA_A_4
  773. [4.888441] HW.GFX.GMA.Registers.Read: 0x04000000 <- 0x00064024:DDI_AUX_DATA_A_5
  774. [4.896369] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  775. [4.902169] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  776. [4.909808] HW.GFX.GMA.Registers.Write: 0x10005000 -> 0x00064014:DDI_AUX_DATA_A_1
  777. [4.917737] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  778. [4.924214] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  779. [4.931851] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064010:DDI_AUX_CTL_A
  780. [4.939492] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  781. [4.948388] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  782. [4.956023] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  783. [4.963951] EDID+0x0000: 00 ff ff ff ff ff ff 00 4d 10 25 14 00 00 00 00
  784. [4.971299] EDID+0x0010: 0d 18 01 04 a5 1d 11 78 06 de 50 a3 54 4c 99 26
  785. [4.978648] EDID+0x0020: 0f 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
  786. [4.985994] EDID+0x0030: 01 01 01 01 01 01 1a 36 80 a0 70 38 1f 40 30 20
  787. [4.993343] EDID+0x0040: 35 00 26 a5 10 00 00 18 54 2b 80 a0 70 38 1f 40
  788. [5.000692] EDID+0x0050: 30 20 35 00 26 a5 10 00 00 18 00 00 00 10 00 00
  789. [5.008040] EDID+0x0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fc
  790. [5.015387] EDID+0x0070: 00 4c 51 31 33 33 4d 31 4a 57 30 38 0a 20 00 04
  791. [5.022736] HW.GFX.GMA.Display_Probing.Read_EDID
  792. [5.027474] HW.GFX.GMA.Power_And_Clocks.PD_On
  793. [5.031921] HW.GFX.GMA.Registers.Read: 0xf0000007 <- 0x00045400:PWR_WELL_CTL_BIOS
  794. [5.039946] HW.GFX.GMA.Registers.Read: 0x7000000f <- 0x00045404:PWR_WELL_CTL_DRIVER
  795. [5.048165] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  796. [5.056189] HW.GFX.GMA.Registers.Read: 0x50000005 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  797. [5.064312] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  798. [5.071951] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  799. [5.079589] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PWR_WELL_CTL_DRIVER
  800. [5.087035] HW.GFX.GMA.Registers.Read: 0x7000000f <- 0x00045404:PWR_WELL_CTL_DRIVER
  801. [5.095252] HW.GFX.GMA.Registers.Write: 0xf000000f -> 0x00045404:PWR_WELL_CTL_DRIVER
  802. [5.103472] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045404:PWR_WELL_CTL_DRIVER
  803. [5.112947] HW.GFX.GMA.Registers.Wait: 0x02000000 <- 0x02000000 & 0x00042000:FUSE_STATUS
  804. [5.121650] HW.GFX.GMA.Power_And_Clocks.PD_On
  805. [5.126097] HW.GFX.GMA.Registers.Read: 0xf0000007 <- 0x00045400:PWR_WELL_CTL_BIOS
  806. [5.134124] HW.GFX.GMA.Registers.Read: 0xf000000f <- 0x00045404:PWR_WELL_CTL_DRIVER
  807. [5.142342] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  808. [5.150369] HW.GFX.GMA.Registers.Read: 0x50000005 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  809. [5.158491] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  810. [5.166130] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  811. [5.173770] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000010 & 0x00045404:PWR_WELL_CTL_DRIVER
  812. [5.183247] HW.GFX.GMA.Registers.Set_Mask: 0x00000020 .S PWR_WELL_CTL_DRIVER
  813. [5.190691] HW.GFX.GMA.Registers.Read: 0xf000000f <- 0x00045404:PWR_WELL_CTL_DRIVER
  814. [5.198913] HW.GFX.GMA.Registers.Write: 0xf000002f -> 0x00045404:PWR_WELL_CTL_DRIVER
  815. [5.207132] HW.GFX.GMA.Registers.Wait: 0x00000010 <- 0x00000010 & 0x00045404:PWR_WELL_CTL_DRIVER
  816. [5.216610] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_B
  817. [5.222410] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064110:DDI_AUX_CTL_B
  818. [5.230049] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064114:DDI_AUX_DATA_B_1
  819. [5.237979] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_B
  820. [5.244458] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064110:DDI_AUX_CTL_B
  821. [5.252097] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064110:DDI_AUX_CTL_B
  822. [5.259737] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064110:DDI_AUX_CTL_B
  823. [5.268634] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
  824. [5.276271] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_B
  825. [5.282073] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
  826. [5.289712] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064114:DDI_AUX_DATA_B_1
  827. [5.297641] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_B
  828. [5.304118] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
  829. [5.311758] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064110:DDI_AUX_CTL_B
  830. [5.319397] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064110:DDI_AUX_CTL_B
  831. [5.328293] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
  832. [5.335931] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_B
  833. [5.341733] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
  834. [5.349371] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064114:DDI_AUX_DATA_B_1
  835. [5.357300] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_B
  836. [5.363779] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
  837. [5.371416] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064110:DDI_AUX_CTL_B
  838. [5.379056] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064110:DDI_AUX_CTL_B
  839. [5.387953] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
  840. [5.395591] HW.GFX.GMA.Display_Probing.Read_EDID
  841. [5.400329] HW.GFX.GMA.Power_And_Clocks.PD_On
  842. [5.404778] HW.GFX.GMA.Registers.Read: 0xf0000017 <- 0x00045400:PWR_WELL_CTL_BIOS
  843. [5.412802] HW.GFX.GMA.Registers.Read: 0xf000003f <- 0x00045404:PWR_WELL_CTL_DRIVER
  844. [5.421020] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  845. [5.429046] HW.GFX.GMA.Registers.Read: 0x50000015 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  846. [5.437169] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  847. [5.444807] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  848. [5.452446] HW.GFX.GMA.Power_And_Clocks.PD_On
  849. [5.456893] HW.GFX.GMA.Registers.Read: 0xf0000017 <- 0x00045400:PWR_WELL_CTL_BIOS
  850. [5.464918] HW.GFX.GMA.Registers.Read: 0xf000003f <- 0x00045404:PWR_WELL_CTL_DRIVER
  851. [5.473137] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  852. [5.481162] HW.GFX.GMA.Registers.Read: 0x50000015 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  853. [5.489284] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  854. [5.496924] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  855. [5.504563] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000040 & 0x00045404:PWR_WELL_CTL_DRIVER
  856. [5.514039] HW.GFX.GMA.Registers.Set_Mask: 0x00000080 .S PWR_WELL_CTL_DRIVER
  857. [5.521484] HW.GFX.GMA.Registers.Read: 0xf000003f <- 0x00045404:PWR_WELL_CTL_DRIVER
  858. [5.529703] HW.GFX.GMA.Registers.Write: 0xf00000bf -> 0x00045404:PWR_WELL_CTL_DRIVER
  859. [5.537922] HW.GFX.GMA.Registers.Wait: 0x00000040 <- 0x00000040 & 0x00045404:PWR_WELL_CTL_DRIVER
  860. [5.547401] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
  861. [5.553202] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064210:DDI_AUX_CTL_C
  862. [5.560841] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064214:DDI_AUX_DATA_C_1
  863. [5.568771] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
  864. [5.575250] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064210:DDI_AUX_CTL_C
  865. [5.582889] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064210:DDI_AUX_CTL_C
  866. [5.590529] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
  867. [5.599426] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064210:DDI_AUX_CTL_C
  868. [5.607064] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064214:DDI_AUX_DATA_C_1
  869. [5.614993] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
  870. [5.620794] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064210:DDI_AUX_CTL_C
  871. [5.628432] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064214:DDI_AUX_DATA_C_1
  872. [5.636362] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00064218:DDI_AUX_DATA_C_2
  873. [5.644292] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
  874. [5.650771] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064210:DDI_AUX_CTL_C
  875. [5.658411] HW.GFX.GMA.Registers.Write: 0xd650023f -> 0x00064210:DDI_AUX_CTL_C
  876. [5.666052] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
  877. [5.674948] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064210:DDI_AUX_CTL_C
  878. [5.682587] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064214:DDI_AUX_DATA_C_1
  879. [5.690518] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
  880. [5.696321] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064210:DDI_AUX_CTL_C
  881. [5.703959] HW.GFX.GMA.Registers.Write: 0x00005000 -> 0x00064214:DDI_AUX_DATA_C_1
  882. [5.711890] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
  883. [5.718368] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064210:DDI_AUX_CTL_C
  884. [5.726007] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064210:DDI_AUX_CTL_C
  885. [5.733648] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
  886. [5.742545] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064210:DDI_AUX_CTL_C
  887. [5.750182] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064214:DDI_AUX_DATA_C_1
  888. [5.758112] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
  889. [5.763913] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064210:DDI_AUX_CTL_C
  890. [5.771553] HW.GFX.GMA.Registers.Write: 0x50005000 -> 0x00064214:DDI_AUX_DATA_C_1
  891. [5.779482] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
  892. [5.785961] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064210:DDI_AUX_CTL_C
  893. [5.793601] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064210:DDI_AUX_CTL_C
  894. [5.801239] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
  895. [5.810136] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064210:DDI_AUX_CTL_C
  896. [5.817775] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064214:DDI_AUX_DATA_C_1
  897. [5.825703] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
  898. [5.831507] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064210:DDI_AUX_CTL_C
  899. [5.839145] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064214:DDI_AUX_DATA_C_1
  900. [5.847074] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
  901. [5.853553] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064210:DDI_AUX_CTL_C
  902. [5.861191] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064210:DDI_AUX_CTL_C
  903. [5.868831] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
  904. [5.877728] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064210:DDI_AUX_CTL_C
  905. [5.885367] HW.GFX.GMA.Registers.Read: 0x0000ffff <- 0x00064214:DDI_AUX_DATA_C_1
  906. [5.893297] HW.GFX.GMA.Registers.Read: 0xffffffff <- 0x00064218:DDI_AUX_DATA_C_2
  907. [5.901227] HW.GFX.GMA.Registers.Read: 0x001e6dfc <- 0x0006421c:DDI_AUX_DATA_C_3
  908. [5.909157] HW.GFX.GMA.Registers.Read: 0x762a9a04 <- 0x00064220:DDI_AUX_DATA_C_4
  909. [5.917088] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064224:DDI_AUX_DATA_C_5
  910. [5.925016] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
  911. [5.930820] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064210:DDI_AUX_CTL_C
  912. [5.938459] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064214:DDI_AUX_DATA_C_1
  913. [5.946390] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
  914. [5.952868] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064210:DDI_AUX_CTL_C
  915. [5.960509] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064210:DDI_AUX_CTL_C
  916. [5.968150] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
  917. [5.977046] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064210:DDI_AUX_CTL_C
  918. [5.984685] HW.GFX.GMA.Registers.Read: 0x00081b01 <- 0x00064214:DDI_AUX_DATA_C_1
  919. [5.992616] HW.GFX.GMA.Registers.Read: 0x04b55725 <- 0x00064218:DDI_AUX_DATA_C_2
  920. [6.000544] HW.GFX.GMA.Registers.Read: 0x789eca95 <- 0x0006421c:DDI_AUX_DATA_C_3
  921. [6.008474] HW.GFX.GMA.Registers.Read: 0xa6554ea1 <- 0x00064220:DDI_AUX_DATA_C_4
  922. [6.016403] HW.GFX.GMA.Registers.Read: 0x26000000 <- 0x00064224:DDI_AUX_DATA_C_5
  923. [6.024333] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
  924. [6.030136] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064210:DDI_AUX_CTL_C
  925. [6.037774] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064214:DDI_AUX_DATA_C_1
  926. [6.045703] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
  927. [6.052182] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064210:DDI_AUX_CTL_C
  928. [6.059823] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064210:DDI_AUX_CTL_C
  929. [6.067465] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
  930. [6.076362] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064210:DDI_AUX_CTL_C
  931. [6.084001] HW.GFX.GMA.Registers.Read: 0x000f5054 <- 0x00064214:DDI_AUX_DATA_C_1
  932. [6.091931] HW.GFX.GMA.Registers.Read: 0x256b8071 <- 0x00064218:DDI_AUX_DATA_C_2
  933. [6.099861] HW.GFX.GMA.Registers.Read: 0x40818081 <- 0x0006421c:DDI_AUX_DATA_C_3
  934. [6.107791] HW.GFX.GMA.Registers.Read: 0xc0a9c0b3 <- 0x00064220:DDI_AUX_DATA_C_4
  935. [6.115721] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064224:DDI_AUX_DATA_C_5
  936. [6.123649] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
  937. [6.129451] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064210:DDI_AUX_CTL_C
  938. [6.137090] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064214:DDI_AUX_DATA_C_1
  939. [6.145021] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
  940. [6.151499] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064210:DDI_AUX_CTL_C
  941. [6.159137] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064210:DDI_AUX_CTL_C
  942. [6.166778] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
  943. [6.175674] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064210:DDI_AUX_CTL_C
  944. [6.183314] HW.GFX.GMA.Registers.Read: 0x00d1c081 <- 0x00064214:DDI_AUX_DATA_C_1
  945. [6.191242] HW.GFX.GMA.Registers.Read: 0x00d1cfd8 <- 0x00064218:DDI_AUX_DATA_C_2
  946. [6.199173] HW.GFX.GMA.Registers.Read: 0xa40020f1 <- 0x0006421c:DDI_AUX_DATA_C_3
  947. [6.207103] HW.GFX.GMA.Registers.Read: 0x40686030 <- 0x00064220:DDI_AUX_DATA_C_4
  948. [6.215032] HW.GFX.GMA.Registers.Read: 0x20000000 <- 0x00064224:DDI_AUX_DATA_C_5
  949. [6.222962] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
  950. [6.228764] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064210:DDI_AUX_CTL_C
  951. [6.236404] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064214:DDI_AUX_DATA_C_1
  952. [6.244335] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
  953. [6.250814] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064210:DDI_AUX_CTL_C
  954. [6.258453] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064210:DDI_AUX_CTL_C
  955. [6.266094] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
  956. [6.274990] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064210:DDI_AUX_CTL_C
  957. [6.282630] HW.GFX.GMA.Registers.Read: 0x007a006a <- 0x00064214:DDI_AUX_DATA_C_1
  958. [6.290561] HW.GFX.GMA.Registers.Read: 0x6e310000 <- 0x00064218:DDI_AUX_DATA_C_2
  959. [6.298491] HW.GFX.GMA.Registers.Read: 0x1a85cf00 <- 0x0006421c:DDI_AUX_DATA_C_3
  960. [6.306419] HW.GFX.GMA.Registers.Read: 0x20f14074 <- 0x00064220:DDI_AUX_DATA_C_4
  961. [6.314350] HW.GFX.GMA.Registers.Read: 0x60000000 <- 0x00064224:DDI_AUX_DATA_C_5
  962. [6.322281] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
  963. [6.328083] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064210:DDI_AUX_CTL_C
  964. [6.335721] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064214:DDI_AUX_DATA_C_1
  965. [6.343651] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
  966. [6.350131] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064210:DDI_AUX_CTL_C
  967. [6.357773] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064210:DDI_AUX_CTL_C
  968. [6.365414] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
  969. [6.374311] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064210:DDI_AUX_CTL_C
  970. [6.381952] HW.GFX.GMA.Registers.Read: 0x0030207a <- 0x00064214:DDI_AUX_DATA_C_1
  971. [6.389883] HW.GFX.GMA.Registers.Read: 0x006a6e31 <- 0x00064218:DDI_AUX_DATA_C_2
  972. [6.397813] HW.GFX.GMA.Registers.Read: 0x00001a00 <- 0x0006421c:DDI_AUX_DATA_C_3
  973. [6.405744] HW.GFX.GMA.Registers.Read: 0x0000fd00 <- 0x00064220:DDI_AUX_DATA_C_4
  974. [6.413676] HW.GFX.GMA.Registers.Read: 0x38000000 <- 0x00064224:DDI_AUX_DATA_C_5
  975. [6.421606] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
  976. [6.427408] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064210:DDI_AUX_CTL_C
  977. [6.435048] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064214:DDI_AUX_DATA_C_1
  978. [6.442979] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
  979. [6.449461] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064210:DDI_AUX_CTL_C
  980. [6.457102] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064210:DDI_AUX_CTL_C
  981. [6.464741] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
  982. [6.473640] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064210:DDI_AUX_CTL_C
  983. [6.481280] HW.GFX.GMA.Registers.Read: 0x004b1e7d <- 0x00064214:DDI_AUX_DATA_C_1
  984. [6.489213] HW.GFX.GMA.Registers.Read: 0x36000a20 <- 0x00064218:DDI_AUX_DATA_C_2
  985. [6.497142] HW.GFX.GMA.Registers.Read: 0x20202020 <- 0x0006421c:DDI_AUX_DATA_C_3
  986. [6.505074] HW.GFX.GMA.Registers.Read: 0x20000000 <- 0x00064220:DDI_AUX_DATA_C_4
  987. [6.513004] HW.GFX.GMA.Registers.Read: 0xfc000000 <- 0x00064224:DDI_AUX_DATA_C_5
  988. [6.520935] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
  989. [6.526738] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064210:DDI_AUX_CTL_C
  990. [6.534379] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064214:DDI_AUX_DATA_C_1
  991. [6.542308] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
  992. [6.548789] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064210:DDI_AUX_CTL_C
  993. [6.556430] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064210:DDI_AUX_CTL_C
  994. [6.564071] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
  995. [6.572968] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064210:DDI_AUX_CTL_C
  996. [6.580607] HW.GFX.GMA.Registers.Read: 0x00004c47 <- 0x00064214:DDI_AUX_DATA_C_1
  997. [6.588538] HW.GFX.GMA.Registers.Read: 0x20554c54 <- 0x00064218:DDI_AUX_DATA_C_2
  998. [6.596468] HW.GFX.GMA.Registers.Read: 0x52415749 <- 0x0006421c:DDI_AUX_DATA_C_3
  999. [6.604400] HW.GFX.GMA.Registers.Read: 0x44450a01 <- 0x00064220:DDI_AUX_DATA_C_4
  1000. [6.612329] HW.GFX.GMA.Registers.Read: 0x71000000 <- 0x00064224:DDI_AUX_DATA_C_5
  1001. [6.620260] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
  1002. [6.626063] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064210:DDI_AUX_CTL_C
  1003. [6.633703] HW.GFX.GMA.Registers.Write: 0x10005000 -> 0x00064214:DDI_AUX_DATA_C_1
  1004. [6.641635] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
  1005. [6.648115] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064210:DDI_AUX_CTL_C
  1006. [6.655755] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064210:DDI_AUX_CTL_C
  1007. [6.663396] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
  1008. [6.672294] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064210:DDI_AUX_CTL_C
  1009. [6.679933] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064214:DDI_AUX_DATA_C_1
  1010. [6.687861] EDID+0x0000: 00 ff ff ff ff ff ff 00 1e 6d fc 76 2a 9a 04 00
  1011. [6.695212] EDID+0x0010: 08 1b 01 04 b5 57 25 78 9e ca 95 a6 55 4e a1 26
  1012. [6.702563] EDID+0x0020: 0f 50 54 25 6b 80 71 40 81 80 81 c0 a9 c0 b3 00
  1013. [6.709913] EDID+0x0030: d1 c0 81 00 d1 cf d8 a4 00 20 f1 40 68 60 30 20
  1014. [6.717264] EDID+0x0040: 7a 00 6a 6e 31 00 00 1a 85 cf 00 20 f1 40 74 60
  1015. [6.724613] EDID+0x0050: 30 20 7a 00 6a 6e 31 00 00 1a 00 00 00 fd 00 38
  1016. [6.731965] EDID+0x0060: 4b 1e 7d 36 00 0a 20 20 20 20 20 20 00 00 00 fc
  1017. [6.739313] EDID+0x0070: 00 4c 47 20 55 4c 54 52 41 57 49 44 45 0a 01 71
  1018. [6.746663] HW.GFX.GMA.Display_Probing.Read_EDID
  1019. [6.751402] HW.GFX.GMA.I2C.I2C_Read
  1020. [6.754884] HW.GFX.GMA.I2C.Init_GMBUS
  1021. [6.758559] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PCH_DSPCLK_GATE_D
  1022. [6.765822] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c2020:PCH_DSPCLK_GATE_D
  1023. [6.773841] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c2020:PCH_DSPCLK_GATE_D
  1024. [6.781876] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2
  1025. [6.790487] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4
  1026. [6.797835] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5
  1027. [6.805186] HW.GFX.GMA.Registers.Write: 0x00000004 -> 0x000c5100:PCH_GMBUS0
  1028. [6.812537] HW.GFX.GMA.I2C.Check_And_Reset
  1029. [6.816697] HW.GFX.GMA.Registers.Read: 0x00008800 <- 0x000c5108:PCH_GMBUS2
  1030. [6.824038] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1
  1031. [6.831398] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
  1032. [7.340013] HW.GFX.GMA.Registers.Wait: Timed Out!
  1033. [7.344670] HW.GFX.GMA.Registers.Read: 0x00008200 <- 0x000c5108:PCH_GMBUS2
  1034. [7.352012] HW.GFX.GMA.I2C.Release_GMBUS
  1035. [7.355977] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0
  1036. [7.363338] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2
  1037. [7.370691] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PCH_DSPCLK_GATE_D
  1038. [7.378137] HW.GFX.GMA.Registers.Read: 0x80000000 <- 0x000c2020:PCH_DSPCLK_GATE_D
  1039. [7.386157] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c2020:PCH_DSPCLK_GATE_D
  1040. [7.394195] HW.GFX.GMA.Display_Probing.Read_EDID
  1041. [7.398925] HW.GFX.GMA.I2C.I2C_Read
  1042. [7.402408] HW.GFX.GMA.I2C.Init_GMBUS
  1043. [7.406084] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PCH_DSPCLK_GATE_D
  1044. [7.413348] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c2020:PCH_DSPCLK_GATE_D
  1045. [7.421368] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c2020:PCH_DSPCLK_GATE_D
  1046. [7.429408] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2
  1047. [7.438018] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4
  1048. [7.445368] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5
  1049. [7.452720] HW.GFX.GMA.Registers.Write: 0x00000005 -> 0x000c5100:PCH_GMBUS0
  1050. [7.460072] HW.GFX.GMA.I2C.Check_And_Reset
  1051. [7.464231] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2
  1052. [7.471573] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c5104:PCH_GMBUS1
  1053. [7.478933] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5104:PCH_GMBUS1
  1054. [7.486295] HW.GFX.GMA.Registers.Read: 0x00008000 <- 0x000c5108:PCH_GMBUS2
  1055. [7.493629] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1
  1056. [7.500990] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
  1057. [7.509609] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2
  1058. [7.516940] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000200 & 0x000c5108:PCH_GMBUS2
  1059. [7.525559] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c5104:PCH_GMBUS1
  1060. [7.532910] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5104:PCH_GMBUS1
  1061. [7.540261] HW.GFX.GMA.I2C.Release_GMBUS
  1062. [7.544217] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0
  1063. [7.551578] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2
  1064. [7.558931] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PCH_DSPCLK_GATE_D
  1065. [7.566379] HW.GFX.GMA.Registers.Read: 0x80000000 <- 0x000c2020:PCH_DSPCLK_GATE_D
  1066. [7.574399] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c2020:PCH_DSPCLK_GATE_D
  1067. [7.582439] HW.GFX.GMA.Power_And_Clocks.PD_Off
  1068. [7.586975] HW.GFX.GMA.Registers.Read: 0xf0000057 <- 0x00045400:PWR_WELL_CTL_BIOS
  1069. [7.595006] HW.GFX.GMA.Registers.Read: 0xf00000ff <- 0x00045404:PWR_WELL_CTL_DRIVER
  1070. [7.603229] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  1071. [7.611256] HW.GFX.GMA.Registers.Read: 0x50000055 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  1072. [7.619382] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  1073. [7.627027] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  1074. [7.634667] HW.GFX.GMA.Power_And_Clocks.PD_Off
  1075. [7.639214] HW.GFX.GMA.Registers.Read: 0xf0000057 <- 0x00045400:PWR_WELL_CTL_BIOS
  1076. [7.647244] HW.GFX.GMA.Registers.Read: 0xf00000ff <- 0x00045404:PWR_WELL_CTL_DRIVER
  1077. [7.655466] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  1078. [7.663497] HW.GFX.GMA.Registers.Read: 0x50000055 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  1079. [7.671622] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  1080. [7.679266] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  1081. [7.686906] HW.GFX.GMA.Registers.Wait: 0x00000040 <- 0x00000040 & 0x00045404:PWR_WELL_CTL_DRIVER
  1082. [7.696387] HW.GFX.GMA.Registers.Unset_Mask: 0x00000080 !S PWR_WELL_CTL_DRIVER
  1083. [7.704029] HW.GFX.GMA.Registers.Read: 0xf00000ff <- 0x00045404:PWR_WELL_CTL_DRIVER
  1084. [7.712251] HW.GFX.GMA.Registers.Write: 0xf000007f -> 0x00045404:PWR_WELL_CTL_DRIVER
  1085. [7.720474] HW.GFX.GMA.Power_And_Clocks.PD_Off
  1086. [7.725020] HW.GFX.GMA.Registers.Read: 0xf0000017 <- 0x00045400:PWR_WELL_CTL_BIOS
  1087. [7.733050] HW.GFX.GMA.Registers.Read: 0xf000003f <- 0x00045404:PWR_WELL_CTL_DRIVER
  1088. [7.741271] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  1089. [7.749299] HW.GFX.GMA.Registers.Read: 0x50000015 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  1090. [7.757426] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  1091. [7.765069] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  1092. [7.772711] HW.GFX.GMA.Registers.Wait: 0x00000010 <- 0x00000010 & 0x00045404:PWR_WELL_CTL_DRIVER
  1093. [7.782192] HW.GFX.GMA.Registers.Unset_Mask: 0x00000020 !S PWR_WELL_CTL_DRIVER
  1094. [7.789833] HW.GFX.GMA.Registers.Read: 0xf000003f <- 0x00045404:PWR_WELL_CTL_DRIVER
  1095. [7.798056] HW.GFX.GMA.Registers.Write: 0xf000001f -> 0x00045404:PWR_WELL_CTL_DRIVER
  1096. [7.806280] HW.GFX.GMA.Power_And_Clocks.PD_Off
  1097. [7.810826] HW.GFX.GMA.Registers.Read: 0xf0000007 <- 0x00045400:PWR_WELL_CTL_BIOS
  1098. [7.818854] HW.GFX.GMA.Registers.Read: 0xf000000f <- 0x00045404:PWR_WELL_CTL_DRIVER
  1099. [7.827078] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  1100. [7.835105] HW.GFX.GMA.Registers.Read: 0x50000005 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  1101. [7.843232] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  1102. [7.850873] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  1103. [7.858516] HW.GFX.GMA.Registers.Wait: 0x00000004 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER
  1104. [7.867997] HW.GFX.GMA.Registers.Unset_Mask: 0x00000008 !S PWR_WELL_CTL_DRIVER
  1105. [7.875636] HW.GFX.GMA.Registers.Read: 0xf000000f <- 0x00045404:PWR_WELL_CTL_DRIVER
  1106. [7.883858] HW.GFX.GMA.Registers.Write: 0xf0000007 -> 0x00045404:PWR_WELL_CTL_DRIVER
  1107. [7.892082] HW.GFX.GMA.Power_And_Clocks.PD_Off
  1108. [7.896629] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS
  1109. [7.904657] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
  1110. [7.912879] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  1111. [7.920908] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  1112. [7.929035] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  1113. [7.936678] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  1114. [7.944318] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045404:PWR_WELL_CTL_DRIVER
  1115. [7.953798] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PWR_WELL_CTL_BIOS
  1116. [7.961246] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS
  1117. [7.969275] HW.GFX.GMA.Registers.Write: 0x70000003 -> 0x00045400:PWR_WELL_CTL_BIOS
  1118. [7.977303] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PWR_WELL_CTL_DRIVER
  1119. [7.984945] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
  1120. [7.993167] HW.GFX.GMA.Registers.Write: 0x70000003 -> 0x00045404:PWR_WELL_CTL_DRIVER
  1121.  
  1122. [8.001584] CONFIG =>
  1123. [8.003712] (Primary =>
  1124. [8.006420] (Port => eDP ,
  1125. [8.009901] Framebuffer =>
  1126. [8.013093] (Width => 1920,
  1127. [8.016963] Height => 1080,
  1128. [8.020832] Start_X => 0,
  1129. [8.024410] Start_Y => 0,
  1130. [8.027990] Stride => 1920,
  1131. [8.031859] V_Stride => 1080,
  1132. [8.035728] Tiling => Linear ,
  1133. [8.039887] Rotation => No_Rotation,
  1134. [8.044434] Offset => 0x00000000,
  1135. [8.048594] BPC => 8),
  1136. [8.051980] Mode =>
  1137. [8.054494] (Dotclock => 138500000,
  1138. [8.059717] H_Visible => 1920,
  1139. [8.064458] H_Sync_Begin => 1968,
  1140. [8.069198] H_Sync_End => 2000,
  1141. [8.073937] H_Total => 2080,
  1142. [8.078676] V_Visible => 1080,
  1143. [8.083416] V_Sync_Begin => 1083,
  1144. [8.088156] V_Sync_End => 1088,
  1145. [8.092895] V_Total => 1111,
  1146. [8.097636] H_Sync_Active_High => False,
  1147. [8.102472] V_Sync_Active_High => False,
  1148. [8.107310] BPC => 8)),
  1149. [8.111953] Secondary =>
  1150. [8.114662] (Port => DP2 ,
  1151. [8.118144] Framebuffer =>
  1152. [8.121335] (Width => 1920,
  1153. [8.125203] Height => 1080,
  1154. [8.129072] Start_X => 0,
  1155. [8.132651] Start_Y => 0,
  1156. [8.136231] Stride => 1920,
  1157. [8.140100] V_Stride => 1080,
  1158. [8.143969] Tiling => Linear ,
  1159. [8.148128] Rotation => No_Rotation,
  1160. [8.152675] Offset => 0x00000000,
  1161. [8.156835] BPC => 8),
  1162. [8.160220] Mode =>
  1163. [8.162734] (Dotclock => 422000000,
  1164. [8.167958] H_Visible => 3840,
  1165. [8.172699] H_Sync_Begin => 3888,
  1166. [8.177438] H_Sync_End => 3920,
  1167. [8.182178] H_Total => 4128,
  1168. [8.186918] V_Visible => 1600,
  1169. [8.191657] V_Sync_Begin => 1607,
  1170. [8.196397] V_Sync_End => 1617,
  1171. [8.201135] V_Total => 1704,
  1172. [8.205877] H_Sync_Active_High => True,
  1173. [8.210616] V_Sync_Active_High => False,
  1174. [8.215452] BPC => 10)),
  1175. [8.220194] Tertiary =>
  1176. [8.222902] (Port => Disabled,
  1177. [8.226384] Framebuffer =>
  1178. [8.229576] (Width => 1,
  1179. [8.233156] Height => 1,
  1180. [8.236735] Start_X => 0,
  1181. [8.240312] Start_Y => 0,
  1182. [8.243891] Stride => 1,
  1183. [8.247470] V_Stride => 1,
  1184. [8.251049] Tiling => Linear ,
  1185. [8.255210] Rotation => No_Rotation,
  1186. [8.259756] Offset => 0x00000000,
  1187. [8.263915] BPC => 8),
  1188. [8.267301] Mode =>
  1189. [8.269815] (Dotclock => 1000000,
  1190. [8.274845] H_Visible => 1,
  1191. [8.279295] H_Sync_Begin => 1,
  1192. [8.283745] H_Sync_End => 1,
  1193. [8.288196] H_Total => 1,
  1194. [8.292644] V_Visible => 1,
  1195. [8.297095] V_Sync_Begin => 1,
  1196. [8.301543] V_Sync_End => 1,
  1197. [8.305994] V_Total => 1,
  1198. [8.310445] H_Sync_Active_High => False,
  1199. [8.315281] V_Sync_Active_High => False,
  1200. [8.320118] BPC => 5)));
  1201. [8.463236] HW.GFX.GMA.PCode.Mailbox_Write_Read
  1202. [8.467696] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
  1203. [8.476307] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA
  1204. [8.484143] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1
  1205. [8.492174] HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX
  1206. [8.499525] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
  1207. [8.508137] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA
  1208. [8.515972] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x0013812c:GT_MAILBOX_DATA_1
  1209. [8.524002] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00138128:GT_MAILBOX_DATA
  1210. [8.531838] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1
  1211. [8.539867] HW.GFX.GMA.PCode.Mailbox_Write_Read
  1212. [8.544511] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA
  1213. [8.552349] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1
  1214. [8.560379] HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX
  1215. [8.567730] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
  1216. [8.576340] HW.GFX.GMA.Registers.Read: 0x00000001 <- 0x00138128:GT_MAILBOX_DATA
  1217. [8.584176] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x0013812c:GT_MAILBOX_DATA_1
  1218. [8.592206] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00138128:GT_MAILBOX_DATA
  1219. [8.600042] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1
  1220. [8.608071] HW.GFX.GMA.Registers.Write: 0x00000382 -> 0x00046000:CDCLK_CTL
  1221. [8.615327] HW.GFX.GMA.PCode.Mailbox_Write_Read
  1222. [8.619969] HW.GFX.GMA.Registers.Write: 0x00000001 -> 0x00138128:GT_MAILBOX_DATA
  1223. [8.627806] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1
  1224. [8.635836] HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX
  1225. [8.643188] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S DBUF_CTL
  1226. [8.649572] HW.GFX.GMA.Registers.Read: 0xc000000a <- 0x00045008:DBUF_CTL
  1227. [8.656731] HW.GFX.GMA.Registers.Write: 0xc000000a -> 0x00045008:DBUF_CTL
  1228. [8.663890] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045008:DBUF_CTL
  1229. [8.672306] HW.GFX.GMA.Power_And_Clocks.PD_On
  1230. [8.676755] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045400:PWR_WELL_CTL_BIOS
  1231. [8.684785] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
  1232. [8.693008] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  1233. [8.701037] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  1234. [8.709164] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  1235. [8.716805] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  1236. [8.724448] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x40000000 & 0x00045404:PWR_WELL_CTL_DRIVER
  1237. [8.733930] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PWR_WELL_CTL_DRIVER
  1238. [8.741380] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
  1239. [8.749601] HW.GFX.GMA.Registers.Write: 0xb0000003 -> 0x00045404:PWR_WELL_CTL_DRIVER
  1240. [8.757824] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045404:PWR_WELL_CTL_DRIVER
  1241. [8.767306] HW.GFX.GMA.Registers.Wait: 0x02000000 <- 0x02000000 & 0x00042000:FUSE_STATUS
  1242. [8.776012] HW.GFX.GMA.Power_And_Clocks.PD_On
  1243. [8.780462] HW.GFX.GMA.Registers.Read: 0x70000003 <- 0x00045400:PWR_WELL_CTL_BIOS
  1244. [8.788491] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
  1245. [8.796714] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  1246. [8.804742] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  1247. [8.812868] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  1248. [8.820509] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  1249. [8.828152] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER
  1250. [8.837632] HW.GFX.GMA.Registers.Set_Mask: 0x00000008 .S PWR_WELL_CTL_DRIVER
  1251. [8.845079] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
  1252. [8.853299] HW.GFX.GMA.Registers.Write: 0xf000000b -> 0x00045404:PWR_WELL_CTL_DRIVER
  1253. [8.861522] HW.GFX.GMA.Registers.Wait: 0x00000004 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER
  1254. [8.871003] HW.GFX.GMA.Power_And_Clocks.PD_On
  1255. [8.875454] HW.GFX.GMA.Registers.Read: 0x70000007 <- 0x00045400:PWR_WELL_CTL_BIOS
  1256. [8.883482] HW.GFX.GMA.Registers.Read: 0xf000000f <- 0x00045404:PWR_WELL_CTL_DRIVER
  1257. [8.891704] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  1258. [8.899733] HW.GFX.GMA.Registers.Read: 0x50000005 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  1259. [8.907858] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  1260. [8.915500] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  1261. [8.923141] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000040 & 0x00045404:PWR_WELL_CTL_DRIVER
  1262. [8.932621] HW.GFX.GMA.Registers.Set_Mask: 0x00000080 .S PWR_WELL_CTL_DRIVER
  1263. [8.940069] HW.GFX.GMA.Registers.Read: 0xf000000f <- 0x00045404:PWR_WELL_CTL_DRIVER
  1264. [8.948292] HW.GFX.GMA.Registers.Write: 0xf000008f -> 0x00045404:PWR_WELL_CTL_DRIVER
  1265. [8.956512] HW.GFX.GMA.Registers.Wait: 0x00000040 <- 0x00000040 & 0x00045404:PWR_WELL_CTL_DRIVER
  1266.  
  1267. [8.966186] Trying to enable port eDP
  1268. [8.970345] HW.GFX.GMA.Connector_Info.Preferred_Link_Setting
  1269. [8.976246] HW.GFX.GMA.Panel.On
  1270. [8.979340] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_PP_CONTROL
  1271. [8.985251] HW.GFX.GMA.Registers.Read: 0x00000003 <- 0x000c7204:PCH_PP_CONTROL
  1272. [8.992979] HW.GFX.GMA.Registers.Set_Mask: 0x00000001 .S PCH_PP_CONTROL
  1273. [8.999951] HW.GFX.GMA.Registers.Read: 0x00000003 <- 0x000c7204:PCH_PP_CONTROL
  1274. [9.007679] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x000c7204:PCH_PP_CONTROL
  1275. [9.015428] HW.GFX.GMA.Panel.Wait_On
  1276. [9.018997] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x30000000 & 0x000c7200:PCH_PP_STATUS
  1277. [9.027907] HW.GFX.GMA.Registers.Unset_Mask: 0x00000008 !S PCH_PP_CONTROL
  1278. [9.035064] HW.GFX.GMA.Registers.Read: 0x00000003 <- 0x000c7204:PCH_PP_CONTROL
  1279. [9.042792] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x000c7204:PCH_PP_CONTROL
  1280. [9.050538] HW.GFX.GMA.DP_Info.Read_Caps
  1281. [9.054495] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1282. [9.060299] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1283. [9.067941] HW.GFX.GMA.Registers.Write: 0x9000000e -> 0x00064014:DDI_AUX_DATA_A_1
  1284. [9.075873] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1285. [9.082355] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1286. [9.089996] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  1287. [9.097640] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1288. [9.106538] HW.GFX.GMA.Registers.Read: 0x4500023f <- 0x00064010:DDI_AUX_CTL_A
  1289. [9.114179] HW.GFX.GMA.Registers.Read: 0x00110a02 <- 0x00064014:DDI_AUX_DATA_A_1
  1290. [9.122111] HW.GFX.GMA.Registers.Read: 0x41000001 <- 0x00064018:DDI_AUX_DATA_A_2
  1291. [9.130041] HW.GFX.GMA.Registers.Read: 0x00020000 <- 0x0006401c:DDI_AUX_DATA_A_3
  1292. [9.137974] HW.GFX.GMA.Registers.Read: 0x00000b00 <- 0x00064020:DDI_AUX_DATA_A_4
  1293.  
  1294. [9.146100] DPCD:
  1295. [9.147841] Rev : 0x11
  1296. [9.151420] Max_Link_Rate : 0x0a
  1297. [9.154998] Max_Lane_Count : 0x02
  1298. [9.158579] TPS3_Supported : 0x00
  1299. [9.162158] Enhanced_Framing: 0x00
  1300. [9.165734] No_Aux_Handshake: 0x40
  1301. [9.169312] Aux_RD_Interval : 0x00
  1302.  
  1303. [9.173084] HW.GFX.GMA.DP_Info.Read_eDP_Rates
  1304. [9.177532] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1305. [9.183336] HW.GFX.GMA.Registers.Read: 0x4500023f <- 0x00064010:DDI_AUX_CTL_A
  1306. [9.190976] HW.GFX.GMA.Registers.Write: 0x90070002 -> 0x00064014:DDI_AUX_DATA_A_1
  1307. [9.198908] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1308. [9.205388] HW.GFX.GMA.Registers.Read: 0x4500023f <- 0x00064010:DDI_AUX_CTL_A
  1309. [9.213029] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  1310. [9.220669] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1311. [9.229567] HW.GFX.GMA.Registers.Read: 0x4440023f <- 0x00064010:DDI_AUX_CTL_A
  1312. [9.237207] HW.GFX.GMA.Registers.Read: 0x0002dd7b <- 0x00064014:DDI_AUX_DATA_A_1
  1313. [9.245137] Trying DP settings: Symbol Rate = 270000000; Lane Count = 2
  1314.  
  1315. [9.252295] HW.GFX.GMA.PLLs.Alloc
  1316. [9.255582] HW.GFX.GMA.Registers.Read: 0x00000043 <- 0x0006c058:DPLL_CTRL1
  1317. [9.262942] HW.GFX.GMA.Connectors.Pre_On
  1318. [9.266896] HW.GFX.GMA.Connectors.DDI.Pre_On
  1319. [9.271249] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DPLL_CTRL2
  1320. [9.277438] HW.GFX.GMA.Registers.Read: 0x00af80c1 <- 0x0006c05c:DPLL_CTRL2
  1321. [9.284787] HW.GFX.GMA.Registers.Write: 0x00af00c1 -> 0x0006c05c:DPLL_CTRL2
  1322. [9.292137] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Train_DP
  1323. [9.298229] HW.GFX.GMA.Registers.Write: 0x80000080 -> 0x00064040:DP_TP_CTL_A
  1324. [9.305677] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  1325. [9.311479] HW.GFX.GMA.Registers.Read: 0x00000091 <- 0x00064000:DDI_BUF_CTL_A
  1326. [9.319118] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_A
  1327. [9.325599] HW.GFX.GMA.Registers.Read: 0x00000091 <- 0x00064000:DDI_BUF_CTL_A
  1328. [9.333239] HW.GFX.GMA.Registers.Write: 0x80000093 -> 0x00064000:DDI_BUF_CTL_A
  1329. [9.340879] HW.GFX.GMA.Registers.Read: 0x80000093 <- 0x00064000:DDI_BUF_CTL_A
  1330. [9.349118] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Init
  1331. [9.355122] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1332. [9.360924] HW.GFX.GMA.Registers.Read: 0x4440023f <- 0x00064010:DDI_AUX_CTL_A
  1333. [9.368563] HW.GFX.GMA.Registers.Write: 0x80010001 -> 0x00064014:DDI_AUX_DATA_A_1
  1334. [9.376491] HW.GFX.GMA.Registers.Write: 0x0a020000 -> 0x00064018:DDI_AUX_DATA_A_2
  1335. [9.384419] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1336. [9.390898] HW.GFX.GMA.Registers.Read: 0x4440023f <- 0x00064010:DDI_AUX_CTL_A
  1337. [9.398537] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A
  1338. [9.406179] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1339. [9.415075] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1340. [9.422715] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1341. [9.430644] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1342. [9.436444] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1343. [9.444085] HW.GFX.GMA.Registers.Write: 0x80010701 -> 0x00064014:DDI_AUX_DATA_A_1
  1344. [9.452016] HW.GFX.GMA.Registers.Write: 0x00010000 -> 0x00064018:DDI_AUX_DATA_A_2
  1345. [9.459945] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1346. [9.466423] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1347. [9.474063] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A
  1348. [9.481701] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1349. [9.490599] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1350. [9.498241] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1351. [9.506169] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Training_Pattern
  1352. [9.513905] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1353. [9.519706] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1354. [9.527343] HW.GFX.GMA.Registers.Write: 0x80010202 -> 0x00064014:DDI_AUX_DATA_A_1
  1355. [9.535273] HW.GFX.GMA.Registers.Write: 0x21000000 -> 0x00064018:DDI_AUX_DATA_A_2
  1356. [9.543201] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1357. [9.549680] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1358. [9.557319] HW.GFX.GMA.Registers.Write: 0xd670023f -> 0x00064010:DDI_AUX_CTL_A
  1359. [9.564961] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1360. [9.573859] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1361. [9.581496] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1362. [9.589525] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  1363. [9.596628] HW.GFX.GMA.DP_Info.Read_Link_Status
  1364. [9.601269] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1365. [9.607072] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1366. [9.614710] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064014:DDI_AUX_DATA_A_1
  1367. [9.622640] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1368. [9.629118] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1369. [9.636757] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  1370. [9.644395] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1371. [9.653292] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1372. [9.660930] HW.GFX.GMA.Registers.Read: 0x00110080 <- 0x00064014:DDI_AUX_DATA_A_1
  1373. [9.668859] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064018:DDI_AUX_DATA_A_2
  1374.  
  1375. [9.676982] Link Status:
  1376. [9.679399] Lane0:
  1377. [9.681430] CR_Done : 1
  1378. [9.684812] Channel_EQ_Done: 0
  1379. [9.688196] Symbol_Locked : 0
  1380. [9.691580] Lane1:
  1381. [9.693609] CR_Done : 1
  1382. [9.696994] Channel_EQ_Done: 0
  1383. [9.700378] Symbol_Locked : 0
  1384. [9.703762] Interlane_Align_Done: 0
  1385. [9.707437] Adjust0:
  1386. [9.709662] Voltage_Swing: 0
  1387. [9.712852] Pre_Emph : 0
  1388. [9.716044] Adjust1:
  1389. [9.718268] Voltage_Swing: 0
  1390. [9.721457] Pre_Emph : 0
  1391.  
  1392. [9.724842] HW.GFX.GMA.Registers.Write: 0x80000180 -> 0x00064040:DP_TP_CTL_A
  1393. [9.732289] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Training_Pattern
  1394. [9.740026] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1395. [9.745827] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1396. [9.753467] HW.GFX.GMA.Registers.Write: 0x80010202 -> 0x00064014:DDI_AUX_DATA_A_1
  1397. [9.761396] HW.GFX.GMA.Registers.Write: 0x22000000 -> 0x00064018:DDI_AUX_DATA_A_2
  1398. [9.769324] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1399. [9.775801] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1400. [9.783441] HW.GFX.GMA.Registers.Write: 0xd670023f -> 0x00064010:DDI_AUX_CTL_A
  1401. [9.791080] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1402. [9.799977] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1403. [9.807615] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1404. [9.815944] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  1405. [9.823012] HW.GFX.GMA.DP_Info.Read_Link_Status
  1406. [9.827654] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1407. [9.833455] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1408. [9.841094] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064014:DDI_AUX_DATA_A_1
  1409. [9.849022] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1410. [9.855502] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1411. [9.863140] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  1412. [9.870779] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1413. [9.879677] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1414. [9.887313] HW.GFX.GMA.Registers.Read: 0x00770081 <- 0x00064014:DDI_AUX_DATA_A_1
  1415. [9.895242] HW.GFX.GMA.Registers.Read: 0x01000000 <- 0x00064018:DDI_AUX_DATA_A_2
  1416.  
  1417. [9.903363] Link Status:
  1418. [9.905781] Lane0:
  1419. [9.907811] CR_Done : 1
  1420. [9.911195] Channel_EQ_Done: 1
  1421. [9.914578] Symbol_Locked : 1
  1422. [9.917960] Lane1:
  1423. [9.919991] CR_Done : 1
  1424. [9.923375] Channel_EQ_Done: 1
  1425. [9.926760] Symbol_Locked : 1
  1426. [9.930142] Interlane_Align_Done: 1
  1427. [9.933816] Adjust0:
  1428. [9.936040] Voltage_Swing: 0
  1429. [9.939230] Pre_Emph : 0
  1430. [9.942419] Adjust1:
  1431. [9.944644] Voltage_Swing: 0
  1432. [9.947835] Pre_Emph : 0
  1433.  
  1434. [9.951218] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Training_Pattern
  1435. [9.958953] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1436. [9.964755] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1437. [9.972392] HW.GFX.GMA.Registers.Write: 0x80010200 -> 0x00064014:DDI_AUX_DATA_A_1
  1438. [9.980322] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00064018:DDI_AUX_DATA_A_2
  1439. [9.988251] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1440. [9.994729] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1441. [10.002367] HW.GFX.GMA.Registers.Write: 0xd650023f -> 0x00064010:DDI_AUX_CTL_A
  1442. [10.010103] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1443. [10.019097] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1444. [10.026831] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1445. [10.034858] HW.GFX.GMA.Registers.Write: 0x80000200 -> 0x00064040:DP_TP_CTL_A
  1446. [10.042399] HW.GFX.GMA.Registers.Write: 0x80000300 -> 0x00064040:DP_TP_CTL_A
  1447. [10.049941] HW.GFX.GMA.Pipe_Setup.On
  1448. [10.053614] HW.GFX.GMA.Transcoder.Setup
  1449. [10.057579] HW.GFX.GMA.Transcoder.Setup_Link
  1450. [10.062025] HW.GFX.GMA.DP_Info.Calculate_M_N
  1451. [10.066474] HW.GFX.GMA.Registers.Write: 0x7e627d27 -> 0x0006f030:PIPE_EDP_DATA_M1
  1452. [10.074499] HW.GFX.GMA.Registers.Write: 0x00800000 -> 0x0006f034:PIPE_EDP_DATA_N1
  1453. [10.082523] HW.GFX.GMA.Registers.Write: 0x00083518 -> 0x0006f040:PIPE_EDP_LINK_M1
  1454. [10.090548] HW.GFX.GMA.Registers.Write: 0x00100000 -> 0x0006f044:PIPE_EDP_LINK_N1
  1455. [10.098573] HW.GFX.GMA.Registers.Write: 0x00000021 -> 0x0006f410:PIPE_EDP_MSA_MISC
  1456. [10.106695] HW.GFX.GMA.Registers.Write: 0x081f077f -> 0x0006f000:HTOTAL_EDP
  1457. [10.114140] HW.GFX.GMA.Registers.Write: 0x081f077f -> 0x0006f004:HBLANK_EDP
  1458. [10.121586] HW.GFX.GMA.Registers.Write: 0x07cf07af -> 0x0006f008:HSYNC_EDP
  1459. [10.128935] HW.GFX.GMA.Registers.Write: 0x04560437 -> 0x0006f00c:VTOTAL_EDP
  1460. [10.136380] HW.GFX.GMA.Registers.Write: 0x04560437 -> 0x0006f010:VBLANK_EDP
  1461. [10.143823] HW.GFX.GMA.Registers.Write: 0x043f043a -> 0x0006f014:VSYNC_EDP
  1462. [10.151175] HW.GFX.GMA.Pipe_Setup.Setup_FB
  1463. [10.155428] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070080:CUR_CTL_A
  1464. [10.162776] HW.GFX.GMA.Registers.Write: 0x80208020 -> 0x00070088:CUR_POS_A
  1465. [10.170123] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070084:CUR_BASE_A
  1466. [10.177569] HW.GFX.GMA.Pipe_Setup.Setup_Display
  1467. [10.182306] HW.GFX.GMA.Registers.Write: 0x009f0008 -> 0x0007027c:PLANE_BUF_CFG_1_A
  1468. [10.190428] HW.GFX.GMA.Registers.Write: 0x80008098 -> 0x00070240:PLANE_WM_1_A_0
  1469. [10.198262] HW.GFX.GMA.Registers.Write: 0x00070000 -> 0x0007017c:CUR_BUF_CFG_A
  1470. [10.205999] HW.GFX.GMA.Registers.Write: 0x80008008 -> 0x00070140:CUR_WM_A_0
  1471. [10.213445] HW.GFX.GMA.Pipe_Setup.Setup_Hires_Plane
  1472. [10.218569] HW.GFX.GMA.Registers.Write: 0x84002000 -> 0x00070180:DSPACNTR
  1473. [10.225824] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000701a4:DSPATILEOFF
  1474. [10.233366] HW.GFX.GMA.Registers.Write: 0x0437077f -> 0x00070190:PLANE_SIZE_1_A
  1475. [10.241199] HW.GFX.GMA.Registers.Write: 0x00000078 -> 0x00070188:DSPASTRIDE
  1476. [10.248645] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007018c:PLANE_POS_1_A
  1477. [10.256380] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007019c:DSPASURF
  1478. [10.263632] HW.GFX.GMA.Registers.Write: 0x077f0437 -> 0x0006001c:PIPEASRC
  1479. [10.270882] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070030:PIPEAMISC
  1480. [10.278231] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PS_CTRL_1_A
  1481. [10.285192] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00068180:PS_CTRL_1_A
  1482. [10.292735] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068180:PS_CTRL_1_A
  1483. [10.300276] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068174:PS_WIN_SZ_1_A
  1484. [10.308011] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PS_CTRL_2_A
  1485. [10.314973] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00068280:PS_CTRL_2_A
  1486. [10.322514] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068280:PS_CTRL_2_A
  1487. [10.330055] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068274:PS_WIN_SZ_2_A
  1488. [10.337789] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070080:CUR_CTL_A
  1489. [10.345138] HW.GFX.GMA.Registers.Write: 0x80208020 -> 0x00070088:CUR_POS_A
  1490. [10.352485] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070084:CUR_BASE_A
  1491. [10.359931] HW.GFX.GMA.Registers.Write: 0x82000002 -> 0x0006f400:PIPE_EDP_DDI_FUNC_CTL
  1492. [10.368440] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x0007f008:PIPE_EDP_CONF
  1493. [10.376173] HW.GFX.GMA.Registers.Read: 0xc0000000 <- 0x0007f008:PIPE_EDP_CONF
  1494. [10.383909] HW.GFX.GMA.Connectors.Post_On
  1495. [10.388066] HW.GFX.GMA.Connectors.DDI.Post_On
  1496. [10.392609] HW.GFX.GMA.Panel.Backlight_On
  1497. [10.396767] HW.GFX.GMA.Registers.Set_Mask: 0x00000004 .S PCH_PP_CONTROL
  1498. [10.403835] HW.GFX.GMA.Registers.Read: 0x00000003 <- 0x000c7204:PCH_PP_CONTROL
  1499. [10.411659] HW.GFX.GMA.Registers.Write: 0x00000007 -> 0x000c7204:PCH_PP_CONTROL
  1500. [10.419500] Enabled port eDP
  1501. [10.422874] HW.GFX.GMA.Power_And_Clocks.PD_On
  1502. [10.427419] HW.GFX.GMA.Registers.Read: 0x70000047 <- 0x00045400:PWR_WELL_CTL_BIOS
  1503. [10.435540] HW.GFX.GMA.Registers.Read: 0xf00000cf <- 0x00045404:PWR_WELL_CTL_DRIVER
  1504. [10.443857] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  1505. [10.451978] HW.GFX.GMA.Registers.Read: 0x50000045 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  1506. [10.460197] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  1507. [10.467935] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  1508. [10.475670] HW.GFX.GMA.Power_And_Clocks.PD_On
  1509. [10.480215] HW.GFX.GMA.Registers.Read: 0x70000047 <- 0x00045400:PWR_WELL_CTL_BIOS
  1510. [10.488337] HW.GFX.GMA.Registers.Read: 0xf00000cf <- 0x00045404:PWR_WELL_CTL_DRIVER
  1511. [10.496652] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  1512. [10.504775] HW.GFX.GMA.Registers.Read: 0x50000045 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  1513. [10.512995] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  1514. [10.520731] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  1515. [10.528464] HW.GFX.GMA.Power_And_Clocks.PD_On
  1516. [10.533010] HW.GFX.GMA.Registers.Read: 0x70000047 <- 0x00045400:PWR_WELL_CTL_BIOS
  1517. [10.541133] HW.GFX.GMA.Registers.Read: 0xf00000cf <- 0x00045404:PWR_WELL_CTL_DRIVER
  1518. [10.549449] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  1519. [10.557571] HW.GFX.GMA.Registers.Read: 0x50000045 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  1520. [10.565790] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  1521. [10.573525] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  1522.  
  1523. [10.581454] Trying to enable port DP2
  1524. [10.585710] HW.GFX.GMA.Connector_Info.Preferred_Link_Setting
  1525. [10.591704] HW.GFX.GMA.DP_Info.Read_Caps
  1526. [10.595764] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
  1527. [10.601663] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064210:DDI_AUX_CTL_C
  1528. [10.609400] HW.GFX.GMA.Registers.Write: 0x9000000e -> 0x00064214:DDI_AUX_DATA_C_1
  1529. [10.617424] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
  1530. [10.623999] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064210:DDI_AUX_CTL_C
  1531. [10.631733] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064210:DDI_AUX_CTL_C
  1532. [10.639469] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
  1533. [10.648462] HW.GFX.GMA.Registers.Read: 0x4500023f <- 0x00064210:DDI_AUX_CTL_C
  1534. [10.656197] HW.GFX.GMA.Registers.Read: 0x001214c4 <- 0x00064214:DDI_AUX_DATA_C_1
  1535. [10.664222] HW.GFX.GMA.Registers.Read: 0x01010001 <- 0x00064218:DDI_AUX_DATA_C_2
  1536. [10.672249] HW.GFX.GMA.Registers.Read: 0x00020206 <- 0x0006421c:DDI_AUX_DATA_C_3
  1537. [10.680274] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064220:DDI_AUX_DATA_C_4
  1538.  
  1539. [10.688493] DPCD:
  1540. [10.690329] Rev : 0x12
  1541. [10.694002] Max_Link_Rate : 0x14
  1542. [10.697676] Max_Lane_Count : 0x04
  1543. [10.701351] TPS3_Supported : 0x40
  1544. [10.705025] Enhanced_Framing: 0x80
  1545. [10.708699] No_Aux_Handshake: 0x00
  1546. [10.712373] Aux_RD_Interval : 0x00
  1547.  
  1548. [10.716240] HW.GFX.GMA.DP_Info.Read_eDP_Rates
  1549. [10.720783] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
  1550. [10.726683] HW.GFX.GMA.Registers.Read: 0x4500023f <- 0x00064210:DDI_AUX_CTL_C
  1551. [10.734416] HW.GFX.GMA.Registers.Write: 0x90070002 -> 0x00064214:DDI_AUX_DATA_C_1
  1552. [10.742442] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
  1553. [10.749017] HW.GFX.GMA.Registers.Read: 0x4500023f <- 0x00064210:DDI_AUX_CTL_C
  1554. [10.756753] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064210:DDI_AUX_CTL_C
  1555. [10.764488] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
  1556. [10.773479] HW.GFX.GMA.Registers.Read: 0x4440023f <- 0x00064210:DDI_AUX_CTL_C
  1557. [10.781215] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064214:DDI_AUX_DATA_C_1
  1558. [10.789239] Trying DP settings: Symbol Rate = 540000000; Lane Count = 4
  1559.  
  1560. [10.796492] HW.GFX.GMA.PLLs.Alloc
  1561. [10.799876] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DPLL_CTRL1
  1562. [10.806160] HW.GFX.GMA.Registers.Read: 0x00000043 <- 0x0006c058:DPLL_CTRL1
  1563. [10.813607] HW.GFX.GMA.Registers.Write: 0x00000043 -> 0x0006c058:DPLL_CTRL1
  1564. [10.821053] HW.GFX.GMA.Registers.Read: 0x00000043 <- 0x0006c058:DPLL_CTRL1
  1565. [10.828498] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x00046014:LCPLL2_CTL
  1566. [10.835942] HW.GFX.GMA.Registers.Wait: 0x00000100 <- 0x00000100 & 0x0006c060:DPLL_STATUS
  1567. [10.844753] HW.GFX.GMA.Connectors.Pre_On
  1568. [10.848804] HW.GFX.GMA.Connectors.DDI.Pre_On
  1569. [10.853251] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DPLL_CTRL2
  1570. [10.859538] HW.GFX.GMA.Registers.Read: 0x00af00c1 <- 0x0006c05c:DPLL_CTRL2
  1571. [10.866985] HW.GFX.GMA.Registers.Write: 0x00ad00c1 -> 0x0006c05c:DPLL_CTRL2
  1572. [10.874431] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Train_DP
  1573. [10.880619] HW.GFX.GMA.Registers.Write: 0x80040080 -> 0x00064240:DP_TP_CTL_C
  1574. [10.888162] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_C
  1575. [10.894061] HW.GFX.GMA.Registers.Read: 0x00000080 <- 0x00064200:DDI_BUF_CTL_C
  1576. [10.901799] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_C
  1577. [10.908375] HW.GFX.GMA.Registers.Read: 0x00000080 <- 0x00064200:DDI_BUF_CTL_C
  1578. [10.916112] HW.GFX.GMA.Registers.Write: 0x80000086 -> 0x00064200:DDI_BUF_CTL_C
  1579. [10.923849] HW.GFX.GMA.Registers.Read: 0x80000086 <- 0x00064200:DDI_BUF_CTL_C
  1580. [10.932188] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Init
  1581. [10.938291] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
  1582. [10.944192] HW.GFX.GMA.Registers.Read: 0x4440023f <- 0x00064210:DDI_AUX_CTL_C
  1583. [10.951931] HW.GFX.GMA.Registers.Write: 0x80010001 -> 0x00064214:DDI_AUX_DATA_C_1
  1584. [10.959958] HW.GFX.GMA.Registers.Write: 0x14840000 -> 0x00064218:DDI_AUX_DATA_C_2
  1585. [10.967987] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
  1586. [10.974565] HW.GFX.GMA.Registers.Read: 0x4440023f <- 0x00064210:DDI_AUX_CTL_C
  1587. [10.982304] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064210:DDI_AUX_CTL_C
  1588. [10.990043] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
  1589. [10.999040] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064210:DDI_AUX_CTL_C
  1590. [11.006779] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064214:DDI_AUX_DATA_C_1
  1591. [11.014807] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
  1592. [11.020709] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064210:DDI_AUX_CTL_C
  1593. [11.028445] HW.GFX.GMA.Registers.Write: 0x80010701 -> 0x00064214:DDI_AUX_DATA_C_1
  1594. [11.036476] HW.GFX.GMA.Registers.Write: 0x00010000 -> 0x00064218:DDI_AUX_DATA_C_2
  1595. [11.044503] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
  1596. [11.051082] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064210:DDI_AUX_CTL_C
  1597. [11.058820] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064210:DDI_AUX_CTL_C
  1598. [11.066561] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
  1599. [11.075558] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064210:DDI_AUX_CTL_C
  1600. [11.083294] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064214:DDI_AUX_DATA_C_1
  1601. [11.091323] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Training_Pattern
  1602. [11.099159] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
  1603. [11.105058] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064210:DDI_AUX_CTL_C
  1604. [11.112797] HW.GFX.GMA.Registers.Write: 0x80010204 -> 0x00064214:DDI_AUX_DATA_C_1
  1605. [11.120825] HW.GFX.GMA.Registers.Write: 0x21000000 -> 0x00064218:DDI_AUX_DATA_C_2
  1606. [11.128854] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0006421c:DDI_AUX_DATA_C_3
  1607. [11.136881] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
  1608. [11.143460] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064210:DDI_AUX_CTL_C
  1609. [11.151197] HW.GFX.GMA.Registers.Write: 0xd690023f -> 0x00064210:DDI_AUX_CTL_C
  1610. [11.158936] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
  1611. [11.167932] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064210:DDI_AUX_CTL_C
  1612. [11.175669] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064214:DDI_AUX_DATA_C_1
  1613. [11.183797] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  1614. [11.190999] HW.GFX.GMA.DP_Info.Read_Link_Status
  1615. [11.195736] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
  1616. [11.201636] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064210:DDI_AUX_CTL_C
  1617. [11.209376] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064214:DDI_AUX_DATA_C_1
  1618. [11.217403] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
  1619. [11.223982] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064210:DDI_AUX_CTL_C
  1620. [11.231719] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064210:DDI_AUX_CTL_C
  1621. [11.239458] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
  1622. [11.248455] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064210:DDI_AUX_CTL_C
  1623. [11.256192] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064214:DDI_AUX_DATA_C_1
  1624. [11.264220] HW.GFX.GMA.Registers.Read: 0x00555500 <- 0x00064218:DDI_AUX_DATA_C_2
  1625.  
  1626. [11.272443] Link Status:
  1627. [11.274957] Lane0:
  1628. [11.277085] CR_Done : 0
  1629. [11.280566] Channel_EQ_Done: 0
  1630. [11.284048] Symbol_Locked : 0
  1631. [11.287532] Lane1:
  1632. [11.289659] CR_Done : 0
  1633. [11.293142] Channel_EQ_Done: 0
  1634. [11.296623] Symbol_Locked : 0
  1635. [11.300104] Lane2:
  1636. [11.302232] CR_Done : 0
  1637. [11.305715] Channel_EQ_Done: 0
  1638. [11.309196] Symbol_Locked : 0
  1639. [11.312678] Lane3:
  1640. [11.314805] CR_Done : 0
  1641. [11.318288] Channel_EQ_Done: 0
  1642. [11.321770] Symbol_Locked : 0
  1643. [11.325250] Interlane_Align_Done: 0
  1644. [11.329023] Adjust0:
  1645. [11.331346] Voltage_Swing: 1
  1646. [11.334634] Pre_Emph : 1
  1647. [11.337922] Adjust1:
  1648. [11.340243] Voltage_Swing: 1
  1649. [11.343533] Pre_Emph : 1
  1650. [11.346821] Adjust2:
  1651. [11.349142] Voltage_Swing: 1
  1652. [11.352432] Pre_Emph : 1
  1653. [11.355721] Adjust3:
  1654. [11.358042] Voltage_Swing: 1
  1655. [11.361329] Pre_Emph : 1
  1656.  
  1657. [11.364811] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_C
  1658. [11.370712] HW.GFX.GMA.Registers.Read: 0x80000006 <- 0x00064200:DDI_BUF_CTL_C
  1659. [11.378451] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_C
  1660. [11.385028] HW.GFX.GMA.Registers.Read: 0x80000006 <- 0x00064200:DDI_BUF_CTL_C
  1661. [11.392767] HW.GFX.GMA.Registers.Write: 0x85000006 -> 0x00064200:DDI_BUF_CTL_C
  1662. [11.400505] HW.GFX.GMA.Registers.Read: 0x85000006 <- 0x00064200:DDI_BUF_CTL_C
  1663. [11.408243] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Signal_Levels
  1664. [11.415789] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
  1665. [11.421690] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064210:DDI_AUX_CTL_C
  1666. [11.429427] HW.GFX.GMA.Registers.Write: 0x80010303 -> 0x00064214:DDI_AUX_DATA_C_1
  1667. [11.437456] HW.GFX.GMA.Registers.Write: 0x09090909 -> 0x00064218:DDI_AUX_DATA_C_2
  1668. [11.445486] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
  1669. [11.452064] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064210:DDI_AUX_CTL_C
  1670. [11.459804] HW.GFX.GMA.Registers.Write: 0xd680023f -> 0x00064210:DDI_AUX_CTL_C
  1671. [11.467544] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
  1672. [11.476539] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064210:DDI_AUX_CTL_C
  1673. [11.484277] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064214:DDI_AUX_DATA_C_1
  1674. [11.492407] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  1675. [11.499608] HW.GFX.GMA.DP_Info.Read_Link_Status
  1676. [11.504346] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
  1677. [11.510248] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064210:DDI_AUX_CTL_C
  1678. [11.517986] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064214:DDI_AUX_DATA_C_1
  1679. [11.526013] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
  1680. [11.532592] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064210:DDI_AUX_CTL_C
  1681. [11.540331] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064210:DDI_AUX_CTL_C
  1682. [11.548068] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
  1683. [11.557063] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064210:DDI_AUX_CTL_C
  1684. [11.564800] HW.GFX.GMA.Registers.Read: 0x00666600 <- 0x00064214:DDI_AUX_DATA_C_1
  1685. [11.572827] HW.GFX.GMA.Registers.Read: 0x00666600 <- 0x00064218:DDI_AUX_DATA_C_2
  1686.  
  1687. [11.581048] Link Status:
  1688. [11.583563] Lane0:
  1689. [11.585690] CR_Done : 0
  1690. [11.589172] Channel_EQ_Done: 1
  1691. [11.592655] Symbol_Locked : 1
  1692. [11.596136] Lane1:
  1693. [11.598265] CR_Done : 0
  1694. [11.601747] Channel_EQ_Done: 1
  1695. [11.605227] Symbol_Locked : 1
  1696. [11.608709] Lane2:
  1697. [11.610838] CR_Done : 0
  1698. [11.614320] Channel_EQ_Done: 1
  1699. [11.617802] Symbol_Locked : 1
  1700. [11.621285] Lane3:
  1701. [11.623411] CR_Done : 0
  1702. [11.626895] Channel_EQ_Done: 1
  1703. [11.630375] Symbol_Locked : 1
  1704. [11.633858] Interlane_Align_Done: 0
  1705. [11.637631] Adjust0:
  1706. [11.639954] Voltage_Swing: 2
  1707. [11.643240] Pre_Emph : 1
  1708. [11.646528] Adjust1:
  1709. [11.648849] Voltage_Swing: 2
  1710. [11.652137] Pre_Emph : 1
  1711. [11.655426] Adjust2:
  1712. [11.657747] Voltage_Swing: 2
  1713. [11.661035] Pre_Emph : 1
  1714. [11.664324] Adjust3:
  1715. [11.666646] Voltage_Swing: 2
  1716. [11.669933] Pre_Emph : 1
  1717.  
  1718. [11.673414] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_C
  1719. [11.679314] HW.GFX.GMA.Registers.Read: 0x85000006 <- 0x00064200:DDI_BUF_CTL_C
  1720. [11.687053] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_C
  1721. [11.693633] HW.GFX.GMA.Registers.Read: 0x85000006 <- 0x00064200:DDI_BUF_CTL_C
  1722. [11.701371] HW.GFX.GMA.Registers.Write: 0x88000006 -> 0x00064200:DDI_BUF_CTL_C
  1723. [11.709108] HW.GFX.GMA.Registers.Read: 0x88000006 <- 0x00064200:DDI_BUF_CTL_C
  1724. [11.716848] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Signal_Levels
  1725. [11.724393] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
  1726. [11.730293] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064210:DDI_AUX_CTL_C
  1727. [11.738034] HW.GFX.GMA.Registers.Write: 0x80010303 -> 0x00064214:DDI_AUX_DATA_C_1
  1728. [11.746061] HW.GFX.GMA.Registers.Write: 0x2e2e2e2e -> 0x00064218:DDI_AUX_DATA_C_2
  1729. [11.754089] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
  1730. [11.760667] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064210:DDI_AUX_CTL_C
  1731. [11.768403] HW.GFX.GMA.Registers.Write: 0xd680023f -> 0x00064210:DDI_AUX_CTL_C
  1732. [11.776141] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
  1733. [11.785139] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064210:DDI_AUX_CTL_C
  1734. [11.792873] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064214:DDI_AUX_DATA_C_1
  1735. [11.801003] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  1736. [11.808203] HW.GFX.GMA.DP_Info.Read_Link_Status
  1737. [11.812941] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
  1738. [11.818840] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064210:DDI_AUX_CTL_C
  1739. [11.826578] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064214:DDI_AUX_DATA_C_1
  1740. [11.834603] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
  1741. [11.841180] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064210:DDI_AUX_CTL_C
  1742. [11.848916] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064210:DDI_AUX_CTL_C
  1743. [11.856652] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
  1744. [11.865646] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064210:DDI_AUX_CTL_C
  1745. [11.873383] HW.GFX.GMA.Registers.Read: 0x00777701 <- 0x00064214:DDI_AUX_DATA_C_1
  1746. [11.881411] HW.GFX.GMA.Registers.Read: 0x03666600 <- 0x00064218:DDI_AUX_DATA_C_2
  1747.  
  1748. [11.889632] Link Status:
  1749. [11.892147] Lane0:
  1750. [11.894275] CR_Done : 1
  1751. [11.897755] Channel_EQ_Done: 1
  1752. [11.901237] Symbol_Locked : 1
  1753. [11.904717] Lane1:
  1754. [11.906846] CR_Done : 1
  1755. [11.910327] Channel_EQ_Done: 1
  1756. [11.913809] Symbol_Locked : 1
  1757. [11.917289] Lane2:
  1758. [11.919417] CR_Done : 1
  1759. [11.922900] Channel_EQ_Done: 1
  1760. [11.926380] Symbol_Locked : 1
  1761. [11.929861] Lane3:
  1762. [11.931987] CR_Done : 1
  1763. [11.935470] Channel_EQ_Done: 1
  1764. [11.938950] Symbol_Locked : 1
  1765. [11.942433] Interlane_Align_Done: 1
  1766. [11.946203] Adjust0:
  1767. [11.948524] Voltage_Swing: 2
  1768. [11.951811] Pre_Emph : 1
  1769. [11.955101] Adjust1:
  1770. [11.957420] Voltage_Swing: 2
  1771. [11.960709] Pre_Emph : 1
  1772. [11.963997] Adjust2:
  1773. [11.966316] Voltage_Swing: 2
  1774. [11.969603] Pre_Emph : 1
  1775. [11.972890] Adjust3:
  1776. [11.975212] Voltage_Swing: 2
  1777. [11.978500] Pre_Emph : 1
  1778.  
  1779. [11.981981] HW.GFX.GMA.Registers.Write: 0x80040480 -> 0x00064240:DP_TP_CTL_C
  1780. [11.989524] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Training_Pattern
  1781. [11.997354] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
  1782. [12.003253] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064210:DDI_AUX_CTL_C
  1783. [12.010988] HW.GFX.GMA.Registers.Write: 0x80010204 -> 0x00064214:DDI_AUX_DATA_C_1
  1784. [12.019017] HW.GFX.GMA.Registers.Write: 0x232e2e2e -> 0x00064218:DDI_AUX_DATA_C_2
  1785. [12.027044] HW.GFX.GMA.Registers.Write: 0x2e000000 -> 0x0006421c:DDI_AUX_DATA_C_3
  1786. [12.035070] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
  1787. [12.041646] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064210:DDI_AUX_CTL_C
  1788. [12.049381] HW.GFX.GMA.Registers.Write: 0xd690023f -> 0x00064210:DDI_AUX_CTL_C
  1789. [12.057115] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
  1790. [12.066109] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064210:DDI_AUX_CTL_C
  1791. [12.073845] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064214:DDI_AUX_DATA_C_1
  1792. [12.082271] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  1793. [12.089436] HW.GFX.GMA.DP_Info.Read_Link_Status
  1794. [12.094173] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
  1795. [12.100073] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064210:DDI_AUX_CTL_C
  1796. [12.107807] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064214:DDI_AUX_DATA_C_1
  1797. [12.115833] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
  1798. [12.122408] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064210:DDI_AUX_CTL_C
  1799. [12.130146] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064210:DDI_AUX_CTL_C
  1800. [12.137881] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
  1801. [12.146873] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064210:DDI_AUX_CTL_C
  1802. [12.154609] HW.GFX.GMA.Registers.Read: 0x00777701 <- 0x00064214:DDI_AUX_DATA_C_1
  1803. [12.162635] HW.GFX.GMA.Registers.Read: 0x03666600 <- 0x00064218:DDI_AUX_DATA_C_2
  1804.  
  1805. [12.170855] Link Status:
  1806. [12.173368] Lane0:
  1807. [12.175495] CR_Done : 1
  1808. [12.178977] Channel_EQ_Done: 1
  1809. [12.182456] Symbol_Locked : 1
  1810. [12.185937] Lane1:
  1811. [12.188065] CR_Done : 1
  1812. [12.191545] Channel_EQ_Done: 1
  1813. [12.195025] Symbol_Locked : 1
  1814. [12.198505] Lane2:
  1815. [12.200633] CR_Done : 1
  1816. [12.204115] Channel_EQ_Done: 1
  1817. [12.207595] Symbol_Locked : 1
  1818. [12.211077] Lane3:
  1819. [12.213204] CR_Done : 1
  1820. [12.216684] Channel_EQ_Done: 1
  1821. [12.220166] Symbol_Locked : 1
  1822. [12.223648] Interlane_Align_Done: 1
  1823. [12.227419] Adjust0:
  1824. [12.229739] Voltage_Swing: 2
  1825. [12.233028] Pre_Emph : 1
  1826. [12.236316] Adjust1:
  1827. [12.238636] Voltage_Swing: 2
  1828. [12.241921] Pre_Emph : 1
  1829. [12.245210] Adjust2:
  1830. [12.247530] Voltage_Swing: 2
  1831. [12.250816] Pre_Emph : 1
  1832. [12.254104] Adjust3:
  1833. [12.256425] Voltage_Swing: 2
  1834. [12.259710] Pre_Emph : 1
  1835.  
  1836. [12.263193] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Training_Pattern
  1837. [12.271024] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
  1838. [12.276922] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064210:DDI_AUX_CTL_C
  1839. [12.284658] HW.GFX.GMA.Registers.Write: 0x80010200 -> 0x00064214:DDI_AUX_DATA_C_1
  1840. [12.292684] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00064218:DDI_AUX_DATA_C_2
  1841. [12.300710] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
  1842. [12.307286] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064210:DDI_AUX_CTL_C
  1843. [12.315022] HW.GFX.GMA.Registers.Write: 0xd650023f -> 0x00064210:DDI_AUX_CTL_C
  1844. [12.322758] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
  1845. [12.331750] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064210:DDI_AUX_CTL_C
  1846. [12.339484] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064214:DDI_AUX_DATA_C_1
  1847. [12.347509] HW.GFX.GMA.Registers.Write: 0x80040200 -> 0x00064240:DP_TP_CTL_C
  1848. [12.355052] HW.GFX.GMA.Registers.Wait: 0x02000000 <- 0x02000000 & 0x00064244:DP_TP_STATUS_C
  1849. [12.364144] HW.GFX.GMA.Registers.Write: 0x80040300 -> 0x00064240:DP_TP_CTL_C
  1850. [12.371686] HW.GFX.GMA.Pipe_Setup.On
  1851. [12.375360] HW.GFX.GMA.Transcoder.Setup
  1852. [12.379323] HW.GFX.GMA.Registers.Write: 0x60000000 -> 0x00046144:TRANSB_CLK_SEL
  1853. [12.387158] HW.GFX.GMA.Transcoder.Setup_Link
  1854. [12.391604] HW.GFX.GMA.DP_Info.Calculate_M_N
  1855. [12.396052] HW.GFX.GMA.Registers.Write: 0x7e5dc71c -> 0x00061030:PIPEB_DATA_M1
  1856. [12.403789] HW.GFX.GMA.Registers.Write: 0x00800000 -> 0x00061034:PIPEB_DATA_N1
  1857. [12.411524] HW.GFX.GMA.Registers.Write: 0x000c80f2 -> 0x00061040:PIPEB_LINK_M1
  1858. [12.419260] HW.GFX.GMA.Registers.Write: 0x00100000 -> 0x00061044:PIPEB_LINK_N1
  1859. [12.426998] HW.GFX.GMA.Registers.Write: 0x00000041 -> 0x00061410:PIPEB_MSA_MISC
  1860. [12.434829] HW.GFX.GMA.Registers.Write: 0x101f0eff -> 0x00061000:HTOTAL_B
  1861. [12.442081] HW.GFX.GMA.Registers.Write: 0x101f0eff -> 0x00061004:HBLANK_B
  1862. [12.449333] HW.GFX.GMA.Registers.Write: 0x0f4f0f2f -> 0x00061008:HSYNC_B
  1863. [12.456491] HW.GFX.GMA.Registers.Write: 0x06a7063f -> 0x0006100c:VTOTAL_B
  1864. [12.463744] HW.GFX.GMA.Registers.Write: 0x06a7063f -> 0x00061010:VBLANK_B
  1865. [12.470998] HW.GFX.GMA.Registers.Write: 0x06500646 -> 0x00061014:VSYNC_B
  1866. [12.478155] HW.GFX.GMA.Pipe_Setup.Setup_FB
  1867. [12.482410] HW.GFX.GMA.Registers.Write: 0x10000000 -> 0x00071080:CUR_CTL_B
  1868. [12.489761] HW.GFX.GMA.Registers.Write: 0x80208020 -> 0x00071088:CUR_POS_B
  1869. [12.497112] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071084:CUR_BASE_B
  1870. [12.504558] HW.GFX.GMA.Pipe_Setup.Setup_Display
  1871. [12.509297] HW.GFX.GMA.Registers.Write: 0x013f00a8 -> 0x0007127c:PLANE_BUF_CFG_1_B
  1872. [12.517421] HW.GFX.GMA.Registers.Write: 0x80008098 -> 0x00071240:PLANE_WM_1_B_0
  1873. [12.525255] HW.GFX.GMA.Registers.Write: 0x00a700a0 -> 0x0007117c:CUR_BUF_CFG_B
  1874. [12.532991] HW.GFX.GMA.Registers.Write: 0x80008008 -> 0x00071140:CUR_WM_B_0
  1875. [12.540438] HW.GFX.GMA.Pipe_Setup.Setup_Hires_Plane
  1876. [12.545562] HW.GFX.GMA.Registers.Write: 0x84002000 -> 0x00071180:DSPBCNTR
  1877. [12.552816] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000711a4:DSPBTILEOFF
  1878. [12.560357] HW.GFX.GMA.Registers.Write: 0x0437077f -> 0x00071190:PLANE_SIZE_1_B
  1879. [12.568192] HW.GFX.GMA.Registers.Write: 0x00000078 -> 0x00071188:DSPBSTRIDE
  1880. [12.575638] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007118c:PLANE_POS_1_B
  1881. [12.583376] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007119c:DSPBSURF
  1882. [12.590629] HW.GFX.GMA.Registers.Write: 0x077f0437 -> 0x0006101c:PIPEBSRC
  1883. [12.597881] HW.GFX.GMA.Registers.Write: 0x00000030 -> 0x00071030:PIPEBMISC
  1884. [12.605231] HW.GFX.GMA.Registers.Write: 0x90000000 -> 0x00068980:PS_CTRL_1_B
  1885. [12.612773] HW.GFX.GMA.Registers.Write: 0x01f20000 -> 0x00068970:PS_WIN_POS_1_B
  1886. [12.620607] HW.GFX.GMA.Registers.Write: 0x0b1c0640 -> 0x00068974:PS_WIN_SZ_1_B
  1887. [12.628342] HW.GFX.GMA.Registers.Write: 0x10000000 -> 0x00071080:CUR_CTL_B
  1888. [12.635694] HW.GFX.GMA.Registers.Write: 0x80208020 -> 0x00071088:CUR_POS_B
  1889. [12.643042] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071084:CUR_BASE_B
  1890. [12.650486] HW.GFX.GMA.Registers.Write: 0xa2115006 -> 0x00061400:PIPEB_DDI_FUNC_CTL
  1891. [12.658705] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x00071008:PIPEBCONF
  1892. [12.666054] HW.GFX.GMA.Registers.Read: 0xc0000000 <- 0x00071008:PIPEBCONF
  1893. [12.673401] HW.GFX.GMA.Connectors.Post_On
  1894. [12.677559] HW.GFX.GMA.Connectors.DDI.Post_On
  1895. [12.682103] Enabled port DP2
  1896. framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
  1897. x_res x y_res: 1920 x 1080, size: 8294400 at 0x80000000
  1898. PCI: 00:02.0 init finished in 10544 msecs
  1899. PCI: 00:04.0 init
  1900. PCI: 00:04.0 init finished in 0 msecs
  1901. PCI: 00:14.0 init
  1902. PCI: 00:14.0 init finished in 0 msecs
  1903. PCI: 00:14.2 init
  1904. PCI: 00:14.2 init finished in 0 msecs
  1905. PCI: 00:15.0 init
  1906. I2C bus 0 version 0x3132312a
  1907. DW I2C bus 0 at 0x9122f000 (400 KHz)
  1908. PCI: 00:15.0 init finished in 6 msecs
  1909. PCI: 00:15.1 init
  1910. I2C bus 1 version 0x3132312a
  1911. DW I2C bus 1 at 0x91230000 (400 KHz)
  1912. PCI: 00:15.1 init finished in 6 msecs
  1913. PCI: 00:1c.0 init
  1914. Initializing PCH PCIe bridge.
  1915. PCI: 00:1c.0 init finished in 3 msecs
  1916. PCI: 00:1d.0 init
  1917. Initializing PCH PCIe bridge.
  1918. PCI: 00:1d.0 init finished in 3 msecs
  1919. PCI: 00:1f.0 init
  1920. IOAPIC: Initializing IOAPIC at 0xfec00000
  1921. IOAPIC: Bootstrap Processor Local APIC = 0x00
  1922. IOAPIC: ID = 0x02
  1923. PCI: 00:1f.0 init finished in 11 msecs
  1924. PCI: 00:1f.3 init
  1925. HDA: codec_mask = 05
  1926. HDA: Initializing codec #2
  1927. HDA: codec viddid: 8086280b
  1928. HDA: No verb table entry found
  1929. HDA: Initializing codec #0
  1930. HDA: codec viddid: 10ec0269
  1931. HDA: verb not loaded
  1932. PCI: 00:1f.3 init finished in 24 msecs
  1933. PCI: 00:1f.4 init
  1934. PCI: 00:1f.4 init finished in 0 msecs
  1935. PCI: 01:00.0 init
  1936. PCI: 01:00.0 init finished in 0 msecs
  1937. PCI: 02:00.0 init
  1938. PCI: 02:00.0 init finished in 0 msecs
  1939. PNP: 004e.0 init
  1940. IT8987: Initializing keyboard.
  1941. PNP: 004e.0 init finished in 11 msecs
  1942. Devices initialized
  1943. BS: BS_DEV_INIT run times (exec / console): 10531 / 176 ms
  1944. FMAP: area SMMSTORE found @ 210000 (262144 bytes)
  1945. SF: Detected 00 0000 with sector size 0x1000, total 0x800000
  1946. smm store: 4 # blocks with size 0x10000
  1947. SMMSTORE: Setting up SMI handler
  1948. BS: BS_DEV_INIT exit times (exec / console): 0 / 18 ms
  1949. Finalize devices...
  1950. PCI: 00:17.0 final
  1951. Devices finalized
  1952. BS: BS_POST_DEVICE run times (exec / console): 0 / 6 ms
  1953. CBFS: Found 'fallback/dsdt.aml' @0x957c0 size 0x3e45 in mcache @0x7abfd1e8
  1954. CBFS: 'fallback/slic' not found.
  1955. ACPI: Writing ACPI tables at 7aa79000.
  1956. ACPI: * FACS
  1957. ACPI: * DSDT
  1958. PCI space above 4GB MMIO is at 0x280000000, len = 0x7d80000000
  1959. ACPI: * FADT
  1960. SCI is IRQ9
  1961. ACPI: added table 1/32, length now 40
  1962. ACPI: * SSDT
  1963. Found 1 CPU(s) with 8 core(s) each.
  1964. PSS: 1801MHz power 15000 control 0x2800 status 0x2800
  1965. PSS: 1800MHz power 15000 control 0x1200 status 0x1200
  1966. PSS: 1800MHz power 15000 control 0x1200 status 0x1200
  1967. PSS: 1600MHz power 13013 control 0x1000 status 0x1000
  1968. PSS: 1400MHz power 11118 control 0xe00 status 0xe00
  1969. PSS: 1200MHz power 9310 control 0xc00 status 0xc00
  1970. PSS: 1000MHz power 7584 control 0xa00 status 0xa00
  1971. PSS: 800MHz power 5920 control 0x800 status 0x800
  1972. PSS: 600MHz power 4335 control 0x600 status 0x600
  1973. PSS: 400MHz power 2820 control 0x400 status 0x400
  1974. PSS: 1801MHz power 15000 control 0x2800 status 0x2800
  1975. PSS: 1800MHz power 15000 control 0x1200 status 0x1200
  1976. PSS: 1800MHz power 15000 control 0x1200 status 0x1200
  1977. PSS: 1600MHz power 13013 control 0x1000 status 0x1000
  1978. PSS: 1400MHz power 11118 control 0xe00 status 0xe00
  1979. PSS: 1200MHz power 9310 control 0xc00 status 0xc00
  1980. PSS: 1000MHz power 7584 control 0xa00 status 0xa00
  1981. PSS: 800MHz power 5920 control 0x800 status 0x800
  1982. PSS: 600MHz power 4335 control 0x600 status 0x600
  1983. PSS: 400MHz power 2820 control 0x400 status 0x400
  1984. PSS: 1801MHz power 15000 control 0x2800 status 0x2800
  1985. PSS: 1800MHz power 15000 control 0x1200 status 0x1200
  1986. PSS: 1800MHz power 15000 control 0x1200 status 0x1200
  1987. PSS: 1600MHz power 13013 control 0x1000 status 0x1000
  1988. PSS: 1400MHz power 11118 control 0xe00 status 0xe00
  1989. PSS: 1200MHz power 9310 control 0xc00 status 0xc00
  1990. PSS: 1000MHz power 7584 control 0xa00 status 0xa00
  1991. PSS: 800MHz power 5920 control 0x800 status 0x800
  1992. PSS: 600MHz power 4335 control 0x600 status 0x600
  1993. PSS: 400MHz power 2820 control 0x400 status 0x400
  1994. PSS: 1801MHz power 15000 control 0x2800 status 0x2800
  1995. PSS: 1800MHz power 15000 control 0x1200 status 0x1200
  1996. PSS: 1800MHz power 15000 control 0x1200 status 0x1200
  1997. PSS: 1600MHz power 13013 control 0x1000 status 0x1000
  1998. PSS: 1400MHz power 11118 control 0xe00 status 0xe00
  1999. PSS: 1200MHz power 9310 control 0xc00 status 0xc00
  2000. PSS: 1000MHz power 7584 control 0xa00 status 0xa00
  2001. PSS: 800MHz power 5920 control 0x800 status 0x800
  2002. PSS: 600MHz power 4335 control 0x600 status 0x600
  2003. PSS: 400MHz power 2820 control 0x400 status 0x400
  2004. PSS: 1801MHz power 15000 control 0x2800 status 0x2800
  2005. PSS: 1800MHz power 15000 control 0x1200 status 0x1200
  2006. PSS: 1800MHz power 15000 control 0x1200 status 0x1200
  2007. PSS: 1600MHz power 13013 control 0x1000 status 0x1000
  2008. PSS: 1400MHz power 11118 control 0xe00 status 0xe00
  2009. PSS: 1200MHz power 9310 control 0xc00 status 0xc00
  2010. PSS: 1000MHz power 7584 control 0xa00 status 0xa00
  2011. PSS: 800MHz power 5920 control 0x800 status 0x800
  2012. PSS: 600MHz power 4335 control 0x600 status 0x600
  2013. PSS: 400MHz power 2820 control 0x400 status 0x400
  2014. PSS: 1801MHz power 15000 control 0x2800 status 0x2800
  2015. PSS: 1800MHz power 15000 control 0x1200 status 0x1200
  2016. PSS: 1800MHz power 15000 control 0x1200 status 0x1200
  2017. PSS: 1600MHz power 13013 control 0x1000 status 0x1000
  2018. PSS: 1400MHz power 11118 control 0xe00 status 0xe00
  2019. PSS: 1200MHz power 9310 control 0xc00 status 0xc00
  2020. PSS: 1000MHz power 7584 control 0xa00 status 0xa00
  2021. PSS: 800MHz power 5920 control 0x800 status 0x800
  2022. PSS: 600MHz power 4335 control 0x600 status 0x600
  2023. PSS: 400MHz power 2820 control 0x400 status 0x400
  2024. PSS: 1801MHz power 15000 control 0x2800 status 0x2800
  2025. PSS: 1800MHz power 15000 control 0x1200 status 0x1200
  2026. PSS: 1800MHz power 15000 control 0x1200 status 0x1200
  2027. PSS: 1600MHz power 13013 control 0x1000 status 0x1000
  2028. PSS: 1400MHz power 11118 control 0xe00 status 0xe00
  2029. PSS: 1200MHz power 9310 control 0xc00 status 0xc00
  2030. PSS: 1000MHz power 7584 control 0xa00 status 0xa00
  2031. PSS: 800MHz power 5920 control 0x800 status 0x800
  2032. PSS: 600MHz power 4335 control 0x600 status 0x600
  2033. PSS: 400MHz power 2820 control 0x400 status 0x400
  2034. PSS: 1801MHz power 15000 control 0x2800 status 0x2800
  2035. PSS: 1800MHz power 15000 control 0x1200 status 0x1200
  2036. PSS: 1800MHz power 15000 control 0x1200 status 0x1200
  2037. PSS: 1600MHz power 13013 control 0x1000 status 0x1000
  2038. PSS: 1400MHz power 11118 control 0xe00 status 0xe00
  2039. PSS: 1200MHz power 9310 control 0xc00 status 0xc00
  2040. PSS: 1000MHz power 7584 control 0xa00 status 0xa00
  2041. PSS: 800MHz power 5920 control 0x800 status 0x800
  2042. PSS: 600MHz power 4335 control 0x600 status 0x600
  2043. PSS: 400MHz power 2820 control 0x400 status 0x400
  2044. \_SB.PCI0.I2C0.H02C: Touchpad at I2C: 00:2c
  2045. \_SB.PCI0.RP01.WF00: WIFI Device PCI: 01:00.0
  2046. ACPI: added table 2/32, length now 44
  2047. ACPI: * MCFG
  2048. ACPI: added table 3/32, length now 48
  2049. ACPI: * LPIT
  2050. ACPI: added table 4/32, length now 52
  2051. ACPI: * MADT
  2052. SCI is IRQ9
  2053. ACPI: added table 5/32, length now 56
  2054. current = 7aa7ed30
  2055. ACPI: * DMAR
  2056. ACPI: added table 6/32, length now 60
  2057. ACPI: added table 7/32, length now 64
  2058. ACPI: * HPET
  2059. ACPI: added table 8/32, length now 68
  2060. ACPI: done.
  2061. ACPI tables: 24176 bytes.
  2062. smbios_write_tables: 7aa78000
  2063. Create SMBIOS type 16
  2064. Create SMBIOS type 17
  2065. PCI: 01:00.0 (WIFI Device)
  2066. SMBIOS tables: 977 bytes.
  2067. Writing table forward entry at 0x00000500
  2068. Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum b534
  2069. Writing coreboot table at 0x7aa9d000
  2070. CBFS: Found 'cmos_layout.bin' @0xfce00 size 0x3ec in mcache @0x7abfd2ac
  2071. 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
  2072. 1. 0000000000001000-000000000009ffff: RAM
  2073. 2. 00000000000a0000-00000000000fffff: RESERVED
  2074. 3. 0000000000100000-000000007aa77fff: RAM
  2075. 4. 000000007aa78000-000000007aaf5fff: CONFIGURATION TABLES
  2076. 5. 000000007aaf6000-000000007abcffff: RAMSTAGE
  2077. 6. 000000007abd0000-000000007affffff: CONFIGURATION TABLES
  2078. 7. 000000007b000000-000000007fffffff: RESERVED
  2079. 8. 00000000e0000000-00000000efffffff: RESERVED
  2080. 9. 00000000fed10000-00000000fed19fff: RESERVED
  2081. 10. 00000000fed80000-00000000fed84fff: RESERVED
  2082. 11. 00000000fed90000-00000000fed91fff: RESERVED
  2083. 12. 0000000100000000-000000027fffffff: RAM
  2084. Wrote coreboot table at: 0x7aa9d000, 0x8b4 bytes, checksum 1649
  2085. coreboot table: 2252 bytes.
  2086. IMD ROOT 0. 0x7afff000 0x00001000
  2087. IMD SMALL 1. 0x7affe000 0x00001000
  2088. FSP MEMORY 2. 0x7abfe000 0x00400000
  2089. RO MCACHE 3. 0x7abfd000 0x000003b8
  2090. CONSOLE 4. 0x7abdd000 0x00020000
  2091. TIME STAMP 5. 0x7abdc000 0x00000910
  2092. ROMSTG STCK 6. 0x7abdb000 0x00001000
  2093. AFTER CAR 7. 0x7abd0000 0x0000b000
  2094. RAMSTAGE 8. 0x7aaf5000 0x000db000
  2095. REFCODE 9. 0x7aac7000 0x0002e000
  2096. SMM BACKUP 10. 0x7aab7000 0x00010000
  2097. 4f444749 11. 0x7aab5000 0x00002000
  2098. 53534d32 12. 0x7aaa5000 0x00010000
  2099. COREBOOT 13. 0x7aa9d000 0x00008000
  2100. ACPI 14. 0x7aa79000 0x00024000
  2101. SMBIOS 15. 0x7aa78000 0x00000800
  2102. IMD small region:
  2103. IMD ROOT 0. 0x7affec00 0x00000400
  2104. FSP RUNTIME 1. 0x7affebe0 0x00000004
  2105. FMAP 2. 0x7affeaa0 0x00000134
  2106. POWER STATE 3. 0x7affea60 0x00000040
  2107. ROMSTAGE 4. 0x7affea40 0x00000004
  2108. MEM INFO 5. 0x7affe860 0x000001e0
  2109. ACPI GNVS 6. 0x7affe760 0x00000100
  2110. BS: BS_WRITE_TABLES run times (exec / console): 3 / 692 ms
  2111. MTRR: Physical address space:
  2112. 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
  2113. 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
  2114. 0x00000000000c0000 - 0x000000007b000000 size 0x7af40000 type 6
  2115. 0x000000007b000000 - 0x0000000080000000 size 0x05000000 type 0
  2116. 0x0000000080000000 - 0x0000000090000000 size 0x10000000 type 1
  2117. 0x0000000090000000 - 0x0000000100000000 size 0x70000000 type 0
  2118. 0x0000000100000000 - 0x0000000280000000 size 0x180000000 type 6
  2119. MTRR: Fixed MSR 0x250 0x0606060606060606
  2120. MTRR: Fixed MSR 0x258 0x0606060606060606
  2121. MTRR: Fixed MSR 0x259 0x0000000000000000
  2122. MTRR: Fixed MSR 0x268 0x0606060606060606
  2123. MTRR: Fixed MSR 0x269 0x0606060606060606
  2124. MTRR: Fixed MSR 0x26a 0x0606060606060606
  2125. MTRR: Fixed MSR 0x26b 0x0606060606060606
  2126. MTRR: Fixed MSR 0x26c 0x0606060606060606
  2127. MTRR: Fixed MSR 0x26d 0x0606060606060606
  2128. MTRR: Fixed MSR 0x26e 0x0606060606060606
  2129. MTRR: Fixed MSR 0x26f 0x0606060606060606
  2130. CPU physical address size: 39 bits
  2131. MTRR: default type WB/UC MTRR counts: 6/6.
  2132. MTRR: UC selected as default type.
  2133. MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
  2134. MTRR: 1 base 0x000000007b000000 mask 0x0000007fff000000 type 0
  2135. MTRR: 2 base 0x000000007c000000 mask 0x0000007ffc000000 type 0
  2136. MTRR: 3 base 0x0000000080000000 mask 0x0000007ff0000000 type 1
  2137. MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6
  2138. MTRR: 5 base 0x0000000200000000 mask 0x0000007f80000000 type 6
  2139. MTRR: Fixed MSR 0x250 0x0606060606060606
  2140. MTRR: Fixed MSR 0x258 0x0606060606060606
  2141. MTRR: Fixed MSR 0x259 0x0000000000000000
  2142. MTRR: Fixed MSR 0x268 0x0606060606060606
  2143. MTRR: Fixed MSR 0x269 0x0606060606060606
  2144. MTRR: Fixed MSR 0x26a 0x0606060606060606
  2145. MTRR: Fixed MSR 0x26b 0x0606060606060606
  2146. MTRR: Fixed MSR 0x26c 0x0606060606060606
  2147. MTRR: Fixed MSR 0x26d 0x0606060606060606
  2148. MTRR: Fixed MSR 0x26e 0x0606060606060606
  2149. MTRR: Fixed MSR 0x26f 0x0606060606060606
  2150. MTRR: Fixed MSR 0x250 0x0606060606060606
  2151. CPU physical address size: 39 bits
  2152. MTRR: Fixed MSR 0x258 0x0606060606060606
  2153. MTRR: Fixed MSR 0x250 0x0606060606060606
  2154. MTRR: Fixed MSR 0x258 0x0606060606060606
  2155. MTRR: Fixed MSR 0x259 0x0000000000000000
  2156. MTRR: Fixed MSR 0x268 0x0606060606060606
  2157. MTRR: Fixed MSR 0x269 0x0606060606060606
  2158. MTRR: Fixed MSR 0x26a 0x0606060606060606
  2159. MTRR: Fixed MSR 0x26b 0x0606060606060606
  2160. MTRR: Fixed MSR 0x26c 0x0606060606060606
  2161. MTRR: Fixed MSR 0x26d 0x0606060606060606
  2162. MTRR: Fixed MSR 0x26e 0x0606060606060606
  2163. MTRR: Fixed MSR 0x26f 0x0606060606060606
  2164. MTRR: Fixed MSR 0x250 0x0606060606060606
  2165. CPU physical address size: 39 bits
  2166. MTRR: Fixed MSR 0x258 0x0606060606060606
  2167. MTRR: Fixed MSR 0x250 0x0606060606060606
  2168.  
  2169. MTRR check
  2170. Fixed MTRRs : Enabled
  2171. Variable MTRRs: Enabled
  2172.  
  2173. MTRR: Fixed MSR 0x258 0x0606060606060606
  2174. MTRR: Fixed MSR 0x259 0x0000000000000000
  2175. MTRR: Fixed MSR 0x268 0x0606060606060606
  2176. MTRR: Fixed MSR 0x269 0x0606060606060606
  2177. MTRR: Fixed MSR 0x26a 0x0606060606060606
  2178. MTRR: Fixed MSR 0x26b 0x0606060606060606
  2179. MTRR: Fixed MSR 0x26c 0x0606060606060606
  2180. MTRR: Fixed MSR 0x26d 0x0606060606060606
  2181. MTRR: Fixed MSR 0x26e 0x0606060606060606
  2182. MTRR: Fixed MSR 0x26f 0x0606060606060606
  2183. BS: BS_WRITE_TABLES exit times (exec / console): 118 / 146 ms
  2184. CPU physical address size: 39 bits
  2185. CBFS: Found 'fallback/payload' @0x126ec0 size 0xb8d7c in mcache @0x7abfd358
  2186. MTRR: Fixed MSR 0x250 0x0606060606060606
  2187. MTRR: Fixed MSR 0x250 0x0606060606060606
  2188. MTRR: Fixed MSR 0x258 0x0606060606060606
  2189. MTRR: Fixed MSR 0x259 0x0000000000000000
  2190. MTRR: Fixed MSR 0x268 0x0606060606060606
  2191. MTRR: Fixed MSR 0x269 0x0606060606060606
  2192. MTRR: Fixed MSR 0x26a 0x0606060606060606
  2193. MTRR: Fixed MSR 0x26b 0x0606060606060606
  2194. MTRR: Fixed MSR 0x26c 0x0606060606060606
  2195. MTRR: Fixed MSR 0x26d 0x0606060606060606
  2196. MTRR: Fixed MSR 0x26e 0x0606060606060606
  2197. MTRR: Fixed MSR 0x26f 0x0606060606060606
  2198. MTRR: Fixed MSR 0x258 0x0606060606060606
  2199. CPU physical address size: 39 bits
  2200. MTRR: Fixed MSR 0x259 0x0000000000000000
  2201. MTRR: Fixed MSR 0x259 0x0000000000000000
  2202. MTRR: Fixed MSR 0x268 0x0606060606060606
  2203. MTRR: Fixed MSR 0x269 0x0606060606060606
  2204. MTRR: Fixed MSR 0x26a 0x0606060606060606
  2205. MTRR: Fixed MSR 0x26b 0x0606060606060606
  2206. MTRR: Fixed MSR 0x26c 0x0606060606060606
  2207. MTRR: Fixed MSR 0x26d 0x0606060606060606
  2208. MTRR: Fixed MSR 0x26e 0x0606060606060606
  2209. MTRR: Fixed MSR 0x26f 0x0606060606060606
  2210. MTRR: Fixed MSR 0x259 0x0000000000000000
  2211. CPU physical address size: 39 bits
  2212. MTRR: Fixed MSR 0x268 0x0606060606060606
  2213. MTRR: Fixed MSR 0x268 0x0606060606060606
  2214. MTRR: Fixed MSR 0x269 0x0606060606060606
  2215. MTRR: Fixed MSR 0x26a 0x0606060606060606
  2216. MTRR: Fixed MSR 0x26b 0x0606060606060606
  2217. MTRR: Fixed MSR 0x26c 0x0606060606060606
  2218. MTRR: Fixed MSR 0x26d 0x0606060606060606
  2219. MTRR: Fixed MSR 0x26e 0x0606060606060606
  2220. MTRR: Fixed MSR 0x26f 0x0606060606060606
  2221. MTRR: Fixed MSR 0x269 0x0606060606060606
  2222. CPU physical address size: 39 bits
  2223. Checking segment from ROM address 0xffb970ec
  2224. MTRR: Fixed MSR 0x26a 0x0606060606060606
  2225. Checking segment from ROM address 0xffb97108
  2226. MTRR: Fixed MSR 0x26b 0x0606060606060606
  2227. MTRR: Fixed MSR 0x26c 0x0606060606060606
  2228. MTRR: Fixed MSR 0x26d 0x0606060606060606
  2229. MTRR: Fixed MSR 0x26e 0x0606060606060606
  2230. MTRR: Fixed MSR 0x26f 0x0606060606060606
  2231. Loading segment from ROM address 0xffb970ec
  2232. CPU physical address size: 39 bits
  2233. code (compression=1)
  2234. New segment dstaddr 0x00800000 memsize 0x800000 srcaddr 0xffb97124 filesize 0xb8d44
  2235. Loading Segment: addr: 0x00800000 memsz: 0x0000000000800000 filesz: 0x00000000000b8d44
  2236. using LZMA
  2237. Loading segment from ROM address 0xffb97108
  2238. Entry Point 0x00803120
  2239. BS: BS_PAYLOAD_LOAD run times (exec / console): 503 / 48 ms
  2240. Finalizing chipset.
  2241. HECI: No CSE device
  2242. apm_control: Finalizing SMM.
  2243. APMC done.
  2244. BS: BS_PAYLOAD_LOAD exit times (exec / console): 4 / 8 ms
  2245. mp_park_aps done after 0 msecs.
  2246. Jumping to boot code at 0x00803120(0x7aa9d000)
  2247.  
  2248.  
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