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  1. ---------------------------------------------------------------------------
  2. -- instruction_memory.vhd - Implementation of A Single-Port, 64 x 32-bit
  3. -- Instruction Memory.
  4. --
  5. -- Modified instruction memory from Lih Wen Koh's Single Cycle Core Processor
  6. ---------------------------------------------------------------------------
  7. library IEEE;
  8. use IEEE.STD_LOGIC_1164.ALL;
  9. use IEEE.STD_LOGIC_ARITH.ALL;
  10. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  11.  
  12. entity instruction_memory is
  13. port ( reset : in std_logic;
  14. clk : in std_logic;
  15. addr_in : in std_logic_vector(5 downto 0);
  16. insn_out : out std_logic_vector(31 downto 0) );
  17. end instruction_memory;
  18.  
  19. architecture behavioral of instruction_memory is
  20.  
  21. type mem_array is array(0 to 63) of std_logic_vector(31 downto 0);
  22. signal sig_insn_mem : mem_array;
  23.  
  24. begin
  25. mem_process: process ( clk,
  26. addr_in ) is
  27.  
  28. variable var_insn_mem : mem_array;
  29. variable var_addr : integer;
  30.  
  31. begin
  32. if (reset = '1') then
  33.  
  34. --Assembly Code
  35. --insn_0 : loop0: addi $1, $0, 70 - $1 <- $0 + 70, i=0, string address starting position
  36. --insn_1 : addi $2, $0, 3 - $2 <- $0 + 3, j=0, pattern address starting position
  37. --insn_2 : load $4, $0, 1 - load data 1($0) into $4, which is the pattern length
  38. --insn_3 : addi $5, $0, 0 - $5 <- $0 + 0, count=0
  39. --insn_4 : addi $6, $0, 0 - $6 <- $0 + 0, k=0, the index of pattern
  40. --insn_5 : addi $9, $0, 0 - $9 <- $0 + 0, the number of matching characters
  41. --insn_6 : load $7, $1, 0 - load data 0($1) into $7, which is a character of string
  42.  
  43. --rd,rs,rt
  44. --insn_7 : beq loop0, $4, $0
  45.  
  46. --insn_8 : noop - avoid data hazard, which is RAW
  47. --insn_9 : noop - avoid data hazard, which is RAW
  48. --
  49. --insn_10 : loop1: bne loop2, $7, $10 - if($7 != 0) go to loop2, not the final character
  50. --insn_11 : beq end, $0, $0 - jump to end, the final character
  51. --
  52. --insn_12 : loop2: addi $2, $0, 3 - $2 <- $0 + 3, pattern position for reset
  53. --insn_13 : addi $6, $0, 0 - $6 <- $0 + 0, pattern index for reset
  54. --
  55. --insn_14 : noop - avoid data hazard, which is RAW
  56. --insn_15 : noop - avoid data hazard, which is RAW
  57. --
  58. --insn_16 : loop7: bne loop3, $6, $4 - pattern index != pattern length
  59. --insn_17 : beq loop6, $6, $4 - pattern index == pattern length
  60. --
  61. --insn_18 : loop3: "80000000" - before load character from string, check testbench signal to allow read character
  62. --insn_19 : load $7, $1, 0 - load data 0($1) into $7, which is the character of string
  63. --insn_20 : load $8, $2, 0 - load data 0($2) into $8, which is the character of pattern
  64. --
  65. --insn_21 : noop - avoid data hazard, which is RAW
  66. --insn_22 : noop - avoid data hazard, which is RAW
  67. --
  68. --insn_23 : beq loop4, $7, $8 - if($7 == $8) go to loop4, character of pattern == character of string
  69. --insn_24 : bne loop5, $7, $8 - if($7 != $8) go to loop5, character of pattern != character of string
  70. --
  71. --insn_25 : loop4: addi $1, $1, 1 - $1 <- $1 + 1, string position ++
  72. --insn_26 : addi $2, $2, 1 - $2 <- $2 + 1, pattern position ++
  73. --insn_27 : addi $6, $6, 1 - $6 <- $6 + 1, pattern index ++
  74. --insn_28 : addi $9, $9, 1 - $9 <- $9 + 1, the number of matching characters ++
  75. --insn_29 : beq loop7, $0, $0 - jump to loop7
  76. --
  77. --insn_30 : loop5: addi $1, $1, 1 - $1 <- $1 + 1, string position ++
  78. --
  79. --insn_31 : noop - avoid data hazard, which is RAW
  80. --insn_32 : noop - avoid data hazard, which is RAW
  81. --
  82. --insn_33 : sub $1, $9, $1 - $1 <- $1 - $9, back to previous position, prevent "AABB"
  83. --insn_34 : addi $9, $0, 0 - $9 <- $0 + 0, reset the value of $9
  84. --insn_35 : beq loop1, $0, $0 - jump to loop1
  85. --
  86. --insn_36 : loop6: load $5, $0, 2 - load 2($0), which is count number into $5 at first for real time
  87. --
  88. --insn_37 noop - avoid data hazard, which is WAW
  89. --insn_38 noop - avoid data hazard, which is WAW
  90. --
  91. --insn_39 addi $5, $5, 1 - $5 <- $5 + 1, count ++
  92. --
  93. --insn_40 : noop - avoid data hazard, which is RAW
  94. --insn_41 : noop - avoid data hazard, which is RAW
  95. --
  96. --insn_42 : store $5, $0, 2 - store data $5 into 2($0) for real time
  97. --insn_43 : addi $9, $0, 0 - $9 <- $0 + 0, reset the value of $9
  98. --insn_44 : beq loop1, $0, $0 - jump to loop1
  99. --
  100. --insn_45 : end: noop - end of program
  101. --insn_46 - insn_63 : noop
  102.  
  103.  
  104. -- 12 decimal to Hex: 12-C; 13-D; 14-E
  105.  
  106. --rs|rt|rd
  107. var_insn_mem(0) := X"40000146";
  108. var_insn_mem(1) := X"40000203";
  109.  
  110. var_insn_mem(2) := X"10000401";
  111.  
  112. var_insn_mem(3) := X"40000500";
  113. var_insn_mem(4) := X"40000600";
  114. var_insn_mem(5) := X"40000900";
  115.  
  116. var_insn_mem(6) := X"10010700";
  117.  
  118. var_insn_mem(7) := X"50040000";
  119.  
  120. var_insn_mem(8) := X"00000000";
  121. var_insn_mem(9) := X"00000000";
  122.  
  123. var_insn_mem(10) := X"60070A0C";
  124. var_insn_mem(11) := X"5000002D";
  125.  
  126. var_insn_mem(12) := X"40000203";
  127. var_insn_mem(13) := X"40000600";
  128.  
  129. var_insn_mem(14) := X"00000000";
  130. var_insn_mem(15) := X"00000000";
  131.  
  132. var_insn_mem(16) := X"60060412";
  133. var_insn_mem(17) := X"50060424";
  134.  
  135. var_insn_mem(18) := X"80000000";
  136.  
  137. var_insn_mem(19) := X"10010700";
  138. var_insn_mem(20) := X"10020800";
  139.  
  140. var_insn_mem(21) := X"00000000";
  141. var_insn_mem(22) := X"00000000";
  142.  
  143. var_insn_mem(23) := X"50070819";
  144. var_insn_mem(24) := X"6007081E";
  145.  
  146. var_insn_mem(25) := X"40010101";
  147. var_insn_mem(26) := X"40020201";
  148. var_insn_mem(27) := X"40060601";
  149. var_insn_mem(28) := X"40090901";
  150.  
  151. var_insn_mem(29) := X"50000010";
  152.  
  153. var_insn_mem(30) := X"40010101";
  154.  
  155. var_insn_mem(31) := X"00000000";
  156. var_insn_mem(32) := X"00000000";
  157.  
  158. var_insn_mem(33) := X"70010901";
  159. var_insn_mem(34) := X"40000900";
  160.  
  161. var_insn_mem(35) := X"5000000A";
  162.  
  163. var_insn_mem(36) := X"10000502";
  164.  
  165. var_insn_mem(37) := X"00000000";
  166. var_insn_mem(38) := X"00000000";
  167.  
  168. var_insn_mem(39) := X"40050501";
  169.  
  170. var_insn_mem(40) := X"00000000";
  171. var_insn_mem(41) := X"00000000";
  172.  
  173. var_insn_mem(42) := X"20000502";
  174.  
  175. var_insn_mem(43) := X"40000900";
  176.  
  177. var_insn_mem(44) := X"5000000A";
  178.  
  179. var_insn_mem(45) := X"00000000";
  180. var_insn_mem(46) := X"00000000";
  181. var_insn_mem(47) := X"00000000";
  182. var_insn_mem(48) := X"00000000";
  183. var_insn_mem(49) := X"00000000";
  184. var_insn_mem(50) := X"00000000";
  185. var_insn_mem(51) := X"00000000";
  186. var_insn_mem(52) := X"00000000";
  187. var_insn_mem(53) := X"00000000";
  188. var_insn_mem(54) := X"00000000";
  189. var_insn_mem(55) := X"00000000";
  190. var_insn_mem(56) := X"00000000";
  191. var_insn_mem(57) := X"00000000";
  192. var_insn_mem(58) := X"00000000";
  193. var_insn_mem(59) := X"00000000";
  194. var_insn_mem(60) := X"00000000";
  195. var_insn_mem(61) := X"00000000";
  196. var_insn_mem(62) := X"00000000";
  197. var_insn_mem(63) := X"00000000";
  198.  
  199.  
  200. elsif (rising_edge(clk)) then
  201. -- read instructions on the rising clock edge
  202. var_addr := conv_integer(addr_in);
  203. insn_out <= var_insn_mem(var_addr);
  204. end if;
  205.  
  206. -- the following are probe signals (for simulation purpose)
  207. sig_insn_mem <= var_insn_mem;
  208.  
  209. end process;
  210.  
  211. end behavioral;
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