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Feb 16th, 2020
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  1. diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py
  2. index 79eaa6d0..91e73c3e 100755
  3. --- a/litex/boards/targets/nexys4ddr.py
  4. +++ b/litex/boards/targets/nexys4ddr.py
  5. @@ -19,6 +19,12 @@ from litedram.phy import s7ddrphy
  6.  from liteeth.phy.rmii import LiteEthPHYRMII
  7.  from liteeth.mac import LiteEthMAC
  8.  
  9. +from litesdcard.phy import SDPHY
  10. +from litesdcard.clocker import SDClockerS7
  11. +from litesdcard.core import SDCore
  12. +from litesdcard.bist import BISTBlockGenerator, BISTBlockChecker
  13. +from litex.soc.cores.timer import Timer
  14. +
  15.  # CRG ----------------------------------------------------------------------------------------------
  16.  
  17.  class _CRG(Module):
  18. @@ -101,6 +107,39 @@ class EthernetSoC(BaseSoC):
  19.              self.ethphy.crg.cd_eth_rx.clk,
  20.              self.ethphy.crg.cd_eth_tx.clk)
  21.  
  22. +# SdSoC -----------------------------------------------------------------------------------------
  23. +
  24. +class SdSoC(EthernetSoC):
  25. +    def __init__(self, **kwargs):
  26. +        EthernetSoC.__init__(self, **kwargs)
  27. +
  28. +        # SDcard
  29. +        sdcard_pads = self.platform.request("sdcard")
  30. +        self.comb += sdcard_pads.rst.eq(0)
  31. +        self.submodules.sdclk = SDClockerS7()
  32. +        self.submodules.sdphy = SDPHY(sdcard_pads, self.platform.device)
  33. +        self.submodules.sdcore = SDCore(self.sdphy)
  34. +        self.submodules.sdtimer = Timer()
  35. +        self.add_csr("sdclk")
  36. +        self.add_csr("sdphy")
  37. +        self.add_csr("sdcore")
  38. +        self.add_csr("sdtimer")
  39. +
  40. +        self.submodules.bist_generator = BISTBlockGenerator(random=True)
  41. +        self.submodules.bist_checker = BISTBlockChecker(random=True)
  42. +        self.add_csr("bist_generator")
  43. +        self.add_csr("bist_checker")
  44. +        self.comb += [
  45. +            self.sdcore.source.connect(self.bist_checker.sink),
  46. +            self.bist_generator.source.connect(self.sdcore.sink)
  47. +        ]
  48. +        self.platform.add_period_constraint(self.sdclk.cd_sd.clk, 1e9/self.clk_freq)
  49. +        self.platform.add_period_constraint(self.sdclk.cd_sd_fb.clk, 1e9/self.clk_freq)
  50. +        self.platform.add_false_path_constraints(
  51. +            self.crg.cd_sys.clk,
  52. +            self.sdclk.cd_sd.clk,
  53. +            self.sdclk.cd_sd_fb.clk)
  54. +
  55.  # Build --------------------------------------------------------------------------------------------
  56.  
  57.  def main():
  58. @@ -113,7 +152,8 @@ def main():
  59.                          help="enable Ethernet support")
  60.      args = parser.parse_args()
  61.  
  62. -    cls = EthernetSoC if args.with_ethernet else BaseSoC
  63. +    #cls = EthernetSoC if args.with_ethernet else BaseSoC
  64. +    cls = SdSoC if args.with_ethernet else BaseSoC
  65.      soc = cls(sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args))
  66.      builder = Builder(soc, **builder_argdict(args))
  67.      builder.build()
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