diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py
index 79eaa6d0..91e73c3e 100755
--- a/litex/boards/targets/nexys4ddr.py
+++ b/litex/boards/targets/nexys4ddr.py
@@ -19,6 +19,12 @@ from litedram.phy import s7ddrphy
 from liteeth.phy.rmii import LiteEthPHYRMII
 from liteeth.mac import LiteEthMAC

+from litesdcard.phy import SDPHY
+from litesdcard.clocker import SDClockerS7
+from litesdcard.core import SDCore
+from litesdcard.bist import BISTBlockGenerator, BISTBlockChecker
+from litex.soc.cores.timer import Timer
+
 # CRG ----------------------------------------------------------------------------------------------

 class _CRG(Module):
@@ -101,6 +107,39 @@ class EthernetSoC(BaseSoC):
             self.ethphy.crg.cd_eth_rx.clk,
             self.ethphy.crg.cd_eth_tx.clk)

+# SdSoC -----------------------------------------------------------------------------------------
+
+class SdSoC(EthernetSoC):
+    def __init__(self, **kwargs):
+        EthernetSoC.__init__(self, **kwargs)
+
+        # SDcard
+        sdcard_pads = self.platform.request("sdcard")
+        self.comb += sdcard_pads.rst.eq(0)
+        self.submodules.sdclk = SDClockerS7()
+        self.submodules.sdphy = SDPHY(sdcard_pads, self.platform.device)
+        self.submodules.sdcore = SDCore(self.sdphy)
+        self.submodules.sdtimer = Timer()
+        self.add_csr("sdclk")
+        self.add_csr("sdphy")
+        self.add_csr("sdcore")
+        self.add_csr("sdtimer")
+
+        self.submodules.bist_generator = BISTBlockGenerator(random=True)
+        self.submodules.bist_checker = BISTBlockChecker(random=True)
+        self.add_csr("bist_generator")
+        self.add_csr("bist_checker")
+        self.comb += [
+            self.sdcore.source.connect(self.bist_checker.sink),
+            self.bist_generator.source.connect(self.sdcore.sink)
+        ]
+        self.platform.add_period_constraint(self.sdclk.cd_sd.clk, 1e9/self.clk_freq)
+        self.platform.add_period_constraint(self.sdclk.cd_sd_fb.clk, 1e9/self.clk_freq)
+        self.platform.add_false_path_constraints(
+            self.crg.cd_sys.clk,
+            self.sdclk.cd_sd.clk,
+            self.sdclk.cd_sd_fb.clk)
+
 # Build --------------------------------------------------------------------------------------------

 def main():
@@ -113,7 +152,8 @@ def main():
                         help="enable Ethernet support")
     args = parser.parse_args()

-    cls = EthernetSoC if args.with_ethernet else BaseSoC
+    #cls = EthernetSoC if args.with_ethernet else BaseSoC
+    cls = SdSoC if args.with_ethernet else BaseSoC
     soc = cls(sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build()