library ieee ;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity vhd is

port( writedata: in std_logic_vector(31 downto 0);

      clk_clk, reset_reset_n:   in std_logic;

      wr, cs : in std_logic;

      pwm_out: out std_logic_vector(1 downto 0);
		hex_out: out std_logic_vector(20 downto 0));

end vhd;

architecture rtl of vhd is

signal reg: std_logic_vector(3 downto 0);

--signal licznik: std_logic_vector(25 downto 0);

begin

process(clk_clk)

begin

   if (clk_clk'event and clk_clk='1') then

      if(wr='1' and cs='1') then

        reg <=writedata(3 downto 0);
        end if;

    end if;

end process;

process(clk_clk)

begin

	if (clk_clk'event and clk_clk='1') then

      --licznik <= licznik +1;

    -- 1 okres=1.34s

      if (reg="0000") then
			pwm_out <= "00";
			hex_out <= "100000010000001000000";

      elsif (reg="0001") then
			pwm_out <= "01";
			hex_out <= "111100101001001000000";

      else
			pwm_out <= "10";
			hex_out <= "000011001011110101111";
      end if;

   end if;

end process;

end rtl;