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LBSC_Thomas_70

Instruction Set for the Slice CPU

Jul 28th, 2017
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  1. Instruction Set for the Slice CPU
  2.  
  3. NOTE: <args> refers to a 4-Bit number, only used in the LD PC instruction, hence the Slice CPU only supports 16 lines of ROM, theoretically it could support up to 65536 lines but I wanna keep it as minimalistic as possible lol. Also, the registers are indexed 1-3, 1 being A, 2 being B and 3 being C.
  4.  
  5. Arithmetic/Logic functions:
  6.  
  7. NOP - 00000
  8. ADD <source reg> <destination reg> - 00001
  9. SUB <source reg> <destination reg> - 00010
  10. AND <source reg> <destination reg> - 00011
  11. OR <source reg> <destination reg> - 00100
  12. XOR <source reg> <destination reg> - 00101
  13. NAND <source reg> <destination reg> - 00101
NOR <source reg> <destination reg> - 00110
  14. XNOR <source reg> <destination reg> - 00111
  15.  
  16. Memory Operations:
  17.  
  18. LD A (ALU) - 01000
  19. LD B (ALU) - 01001
  20. LD C (ALU) - 01010
  21. LD A <args> - 01011
  22. LD B <args> - 01100
  23. LD C <args> - 01101
  24. MOV <source reg> <destination reg> - 01110
  25.  
  26. Flag Controls:
  27.  
  28. JMP <args> - 01111
  29. NEG <args> - 10000
  30. COUT <args> - 10001
  31. !ZR <args> - 10010
  32. ZR <args> - 10011
  33.  
  34. Program Counter Operations:
  35.  
  36. LD PC <args> - 10100
  37. RST PC - 10101
  38.  
  39. Additional Operations:
  40. HLT - 10110
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