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- `timescale 1ns / 1ps
- //////////////////////////////////////////////////////////////////////////////////
- // Company:
- // Engineer:
- //
- // Create Date:
- // Design Name:
- // Module Name:
- // Project Name:
- // Target Devices:
- // Tool Versions:
- // Description:
- //
- // Dependencies:
- //
- // Revision:
- // Revision 0.01 - File Created
- // Additional Comments:
- //
- //////////////////////////////////////////////////////////////////////////////////
- module crt(
- input clk,
- input rst,
- input start,
- input [7:0] x_in,
- output busy,
- output reg [7:0] y_out
- );
- // states
- localparam idle = 4'b0000;
- localparam next = 4'b0001;
- localparam reset = 4'b0010;
- localparam y_double_mul_ready = 4'b0011;
- localparam y_triple_mul_start = 4'b0100;
- localparam y_triple_mul_ready = 4'b0101;
- localparam y_inc_b_mul_start = 4'b0110;
- localparam y_inc_b_mul_ready = 4'b0111;
- localparam b_inc_and_shift = 4'b1000;
- localparam x_b_condition = 4'b1001;
- localparam loop = 4'b1010;
- reg [3:0] state, next_state;
- reg [7:0] y, b, x;
- reg [7:0] a_mul1, b_mul1;
- reg start_mul1;
- wire [7:0] result_mul1;
- reg reset_mul1;
- wire busy_mul1;
- reg [4:0] counter;
- wire [4:0] end_step;
- mult mul1(
- .clk_i(clk),
- .rst_i(reset_mul1),
- .a_bi(a_mul1),
- .b_bi(b_mul1),
- .start_i(start_mul1),
- .busy_o(busy_mul1),
- .y_bo(result_mul1)
- );
- assign busy = (state != idle);
- assign end_step = (counter == 5'd0);
- always@ (posedge clk)
- if(rst)begin
- counter <= 6;
- y_out <= 0;
- y <= 0;
- state <= idle;
- end else begin
- case (state)
- reset:
- begin
- reset_mul1 <= 0;
- state <= next;
- end
- next:
- begin
- state <= next_state;
- end
- idle:
- if(start) begin // starting y * 2 mul process
- state <= reset;
- next_state <= y_double_mul_ready;
- counter <= 6;
- y <= 0;
- x <= x_in;
- reset_mul1 <= 1;
- start_mul1 <= 1;
- a_mul1 <= 2;
- b_mul1 <= y;
- end
- y_double_mul_ready: // y = 2 * y
- if(!busy_mul1) begin
- state <= y_triple_mul_start;
- start_mul1 <= 0;
- y <= result_mul1;
- end
- y_triple_mul_start: // starting y * 3 mul process
- begin
- state <= reset;
- next_state <= y_triple_mul_ready;
- reset_mul1 <= 1;
- start_mul1 <= 1;
- a_mul1 <= y;
- b_mul1 <= 3;
- end
- y_triple_mul_ready: // b = y * 3
- if(!busy_mul1) begin
- state <= y_inc_b_mul_start;
- start_mul1 <= 0;
- b <= result_mul1;
- end
- y_inc_b_mul_start: // starting b*(y+1) or 3*y*(y+1) mul process
- begin
- state <= reset;
- next_state <= y_inc_b_mul_ready;
- reset_mul1 <= 1;
- start_mul1 <= 1;
- a_mul1 <= y+1;
- b_mul1 <= b;
- end
- y_inc_b_mul_ready: // b = 3*y*(y+1)
- if(!busy_mul1) begin
- state <= b_inc_and_shift;
- b <= result_mul1;
- end
- b_inc_and_shift: // b = (3*y*(y+1))+1 << counter
- begin
- state <= x_b_condition;
- b <= (b+1) << counter;
- end
- x_b_condition: // checking for x >= b and doing operations according to algorithm
- if( x >= b ) begin
- state <= loop;
- x <= x - b;
- y <= y + 1;
- end else begin
- state <= loop;
- end
- loop: // starting again or finishing calculation
- begin
- if (end_step) begin // finishing calculation
- state <= idle;
- y_out <= y;
- end else begin // starting again
- counter <= counter-3;
- state <= reset;
- next_state <= y_double_mul_ready;
- a_mul1 <= 2; // starting y * 2 mul process again
- b_mul1 <= y;
- reset_mul1 <= 1;
- end
- end
- endcase
- end
- endmodule
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