module Lab4(
                input [17:0] SW,
                output reg [17:0] LEDR
);


    initial begin
        LEDR = 18'b0;
    end

    always @(SW[8:0])
        begin
            //on for addition
            if(SW[8]) begin
                LEDR[3:0] = SW[3:0] + SW[7:4];
                if(SW[3] == SW[7] && LEDR[3] != SW[3])
                        LEDR[17] = 1;
                else
                        LEDR[17] = 0;
            end
            else begin
                LEDR[3:0] = SW[7:4] + (~SW[3:0]+ 4'b0001);
                if(SW[3] != SW[7] && LEDR[3] != SW[7])
                        LEDR[17] = 1;
                    else
                        LEDR[17] = 0;
            end
        end
endmodule