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Jun 19th, 2018
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  1. DefinitionBlock ("msispeedstep.aml", "DSDT", 1, "A7512", "A7512100", 0x00000100)
  2. {
  3. External (PDC0)
  4. External (CFGD)
  5.  
  6. Scope (_PR)
  7. {
  8. Processor (P001, 0x01, 0x00000810, 0x06)
  9. {
  10. Method (_CST, 0, NotSerialized)
  11. {
  12. If (LAnd (And (CFGD, 0x01000000), LNot (And (PDC0, 0x10
  13. ))))
  14. {
  15. Return (Package (0x02)
  16. {
  17. One,
  18. Package (0x04)
  19. {
  20. ResourceTemplate ()
  21. {
  22. Register (FFixedHW,
  23. 0x00, // Bit Width
  24. 0x00, // Bit Offset
  25. 0x0000000000000000, // Address
  26. ,)
  27. },
  28.  
  29. One,
  30. 0x9D,
  31. 0x03E8
  32. }
  33. })
  34. }
  35.  
  36. If (And (PDC0, 0x0300))
  37. {
  38. If (And (CFGD, 0x20))
  39. {
  40. Return (Package (0x03)
  41. {
  42. 0x02,
  43. Package (0x04)
  44. {
  45. ResourceTemplate ()
  46. {
  47. Register (FFixedHW,
  48. 0x01, // Bit Width
  49. 0x02, // Bit Offset
  50. 0x0000000000000000, // Address
  51. ,)
  52. },
  53.  
  54. One,
  55. One,
  56. 0x03E8
  57. },
  58.  
  59. Package (0x04)
  60. {
  61. ResourceTemplate ()
  62. {
  63. Register (FFixedHW,
  64. 0x01, // Bit Width
  65. 0x02, // Bit Offset
  66. 0x0000000000000010, // Address
  67. ,)
  68. },
  69.  
  70. 0x02,
  71. One,
  72. 0x01F4
  73. }
  74. })
  75. }
  76. }
  77.  
  78. If (And (CFGD, 0x20))
  79. {
  80. Return (Package (0x03)
  81. {
  82. 0x02,
  83. Package (0x04)
  84. {
  85. ResourceTemplate ()
  86. {
  87. Register (FFixedHW,
  88. 0x01, // Bit Width
  89. 0x02, // Bit Offset
  90. 0x0000000000000000, // Address
  91. ,)
  92. },
  93.  
  94. One,
  95. One,
  96. 0x03E8
  97. },
  98.  
  99. Package (0x04)
  100. {
  101. ResourceTemplate ()
  102. {
  103. Register (SystemIO,
  104. 0x08, // Bit Width
  105. 0x00, // Bit Offset
  106. 0x000000000000000C, // Address
  107. ,)
  108. },
  109.  
  110. 0x02,
  111. One,
  112. 0x01F4
  113. }
  114. })
  115. }
  116.  
  117. Return (Package (0x02)
  118. {
  119. One,
  120. Package (0x04)
  121. {
  122. ResourceTemplate ()
  123. {
  124. Register (FFixedHW,
  125. 0x01, // Bit Width
  126. 0x02, // Bit Offset
  127. 0x0000000000000000, // Address
  128. ,)
  129. },
  130.  
  131. One,
  132. One,
  133. 0x03E8
  134. }
  135. })
  136. }
  137. }
  138.  
  139. Processor (P002, 0x02, 0x00000000, 0x00)
  140. {
  141. Method (_CST, 0, NotSerialized)
  142. {
  143. Return (^^P001._CST ())
  144. }
  145. }
  146.  
  147. Processor (P003, 0x03, 0x00000000, 0x00)
  148. {
  149. Method (_CST, 0, NotSerialized)
  150. {
  151. Return (^^P001._CST ())
  152. }
  153. }
  154.  
  155. Processor (P004, 0x04, 0x00000000, 0x00)
  156. {
  157. Method (_CST, 0, NotSerialized)
  158. {
  159. Return (^^P001._CST ())
  160. }
  161. }
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