DD lab 5

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sv_seg is
port (bcd : in std_logic_vector(3 downto 0);  		--BCD input
        segment7 : out std_logic_vector(6 downto 0));  	-- 7 bit decoded output.;
end sv_seg;

architecture behavior of sv_seg is
BEGIN
	segment7 <= "1000000" when bcd = "0000" else
					"1111001" when bcd = "0001" else
					"0100100" when bcd = "0010" else
					"0110000" when bcd = "0011" else
			 		"0011001" when bcd = "0100" else
					"0010010" when bcd = "0101" else
					"0000010" when bcd = "0110" else
					"1111000" when bcd = "0111" else
					"0000000" when bcd = "1000" else
					"0010000" when bcd = "1001" else
					"-------";
end behavior;




library IEEE;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_1164.ALL;


entity sorter is
	port( clk,sort,reset : in std_logic ;
			weight	: in std_logic_vector(9 downto 0);
			grp1, grp2, grp3, grp4 : buffer std_logic_vector(3 downto 0);
			seg1, seg2, seg3, seg4 : out std_logic_vector (6 downto 0);
			cur_grp : out std_logic_vector ( 2 downto 0));
	end sorter;


Architecture ps_behavior of sorter is

	signal l_sort : std_logic :='1';
	component sv_seg
		port( bcd : in std_logic_vector (3 downto 0);
				 segment7: out std_logic_vector (6 downto 0));
	end component;

Begin

	s7a: sv_seg port map (grp1,seg1);
	s7b: sv_seg port map (grp2,seg2);
	s7c: sv_seg port map (grp3,seg3);
	s7d: sv_seg port map (grp4,seg4);

		process(clk, sort, reset)
		begin

			if (reset = '0') then
			grp1 <= (others => '0' );
			grp2 <= (others => '0' );
			grp3 <= (others => '0' );
			grp4 <= (others => '0' );
			cur_grp <= (others => '0');
			elsif (clk'event and clk = '1') then
			if (sort = '1' and l_sort = '0') then
		    if (weight > 800) then
				grp4 <= 1 + grp4;
				cur_grp <= "100";
				elsif (weight > 500) then
				grp3 <= 1 + grp3;
				cur_grp <= "011";
				elsif (weight > 200) then
				grp2 <= 1 + grp2;
				cur_grp <= "010";
				elsif (weight > 0) then
				grp1 <= 1 + grp1;
				cur_grp <= "001";
				else cur_grp <= (others => '0');
				end if;
			end if;
			l_sort <= sort;
		end if;
	   end process;
		end ps_behavior;