muts@Rishu-Inspiron-3543:~/RISE/gem5$ build/RISCV/gem5.opt configs/multi_core/two_core/two_core_copy.py
gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 compiled Feb 25 2019 15:54:17
gem5 started Mar  1 2019 17:22:16
gem5 executing on Rishu-Inspiron-3543, pid 10033
command line: build/RISCV/gem5.opt configs/multi_core/two_core/two_core_copy.py

Version of python is :::::::::::: 2.7.12 (default, Nov 12 2018, 14:36:49)
[GCC 5.4.0 20160609]
[<m5.objects.TimingSimpleCPU.TimingSimpleCPU object at 0x7fd46e84c190>]
[<m5.objects.TimingSimpleCPU.TimingSimpleCPU object at 0x7fd46e84c4d0>]
<orphan System>.cpu0
<orphan System>.cpu1
Global frequency set at 1000000000000 ticks per second
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
warn: Unknown operating system; assuming Linux.
warn: Unknown operating system; assuming Linux.
0: system.remote_gdb: listening for remote gdb on port 7000
0: system.remote_gdb: listening for remote gdb on port 7001
The simulation is going to start in 3 2 1 .. GOOOO!
info: Entering event queue @ 0.  Starting simulation...
mHART ID is 0 and mstatus is is 8192 and archid is 0
mHART ID is 0 and mstatus is is 8192 and archid is 0
Exiting @ tick 29102000 because exiting with last active thread context