library ieee;
use ieee.std_logic_1164.all;
entity AUT2 is port	(
	CLK,RESET,UP:			in std_logic;
	Q:				out std_logic_vector(0 to 2);
	Y:				out std_logic
	);
end AUT2;

architecture  arch_of_AUT2 of AUT2 is
	type states is (state0, state1, state2, state3, state4, state5);
    -- directiva care specific? implementarea automatului secven?ial de tip "one-hot-one"
attribute state_encoding of states: type is one_hot_one;

signal state: states;
begin
process  (CLK)
	begin
	if (CLK'event and CLK='0') then
		if  RESET ='1'  then
		state <= state0;
else
			case state is
				when state0 =>
					if  UP = '1'  then
						state <= state1;
					else
						state <= state5;
					end if;
				when state1 =>
					if  UP = '1'  then
						state <= state2;
					else
						state <= state0;
					end if;
				when state2 =>
					if  UP = '1'  then
						state <= state3;
					else
						state <= state1;
					end if;
				when state3 =>
					if  UP = '1'  then
						state <= state4;
					else
						state <= state2;
					end if;
				when state4 =>
					if  UP = '1'  then
						state <= state5;
					else
						state <= state3;
					end if;
				when state5 =>
					if  UP = '1'  then
						state <= state0;
					else
						state <= state4;
					end if;
				end case;
		end if;
end if;
end process;
---IESIRE DE TIP MOORE
Q <= 	"001"	when  (state=state0)	else
"011"	when  (state=state1) 	else
	"010"	when  (state=state2) 	else
	"110"	when  (state=state3) 	else
	"111"	when  (state=state4) 	else
	"101";
---IESIRE DE TIP MEALY
Y <= 	'1'	when  (state = state2 and UP='1' )	else
	'0';

end arch_of_AUT2;