#include "stm32f1xx.h"

//GPIO_InitTypeDef GPIO_InitStructure;
unsigned int delayer = 100000;

void delay(unsigned long p)
{
	unsigned long i;
	for(i = 0; i < p ; i++);
}

int main()
{
	RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_TIM1EN | RCC_APB2ENR_AFIOEN;
	//PAx push-pull
	GPIOA->CRH &= ~GPIO_CRH_CNF9;
	GPIOA->CRH |= GPIO_CRH_CNF9_1;
	GPIOA->CRH &= ~GPIO_CRH_MODE9;
	GPIOA->CRH |= GPIO_CRH_MODE9_1;

	GPIOA->CRH &= ~GPIO_CRH_CNF10;
	GPIOA->CRH |= GPIO_CRH_CNF10_1;
	GPIOA->CRH &= ~GPIO_CRH_MODE10;
	GPIOA->CRH |= GPIO_CRH_MODE10_1;

	GPIOA->CRH &= ~GPIO_CRH_CNF11;
	GPIOA->CRH |= GPIO_CRH_CNF11_1;
	GPIOA->CRH &= ~GPIO_CRH_MODE11;
	GPIOA->CRH |= GPIO_CRH_MODE11_1;

	TIM1->PSC = 72;
	TIM1->ARR = 255;

	TIM1->CCR2 = 0;
	TIM1->CCR3 = 0;
	TIM1->CCR4 = 0;

	TIM1->CCER |= TIM_CCER_CC4E | TIM_CCER_CC4P;
	TIM1->CCER |= TIM_CCER_CC3E | TIM_CCER_CC3P;
	TIM1->CCER |= TIM_CCER_CC2E | TIM_CCER_CC2P;

	TIM1->BDTR |= TIM_BDTR_MOE;

	TIM1->CCMR2 |= TIM_CCMR2_OC4M_2 | TIM_CCMR2_OC4M_1;
	TIM1->CCMR2 |= TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_1;
	TIM1->CCMR1 |= TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2M_1;

	TIM1->CR1 &= ~TIM_CR1_DIR;
	TIM1->CR1 &= ~TIM_CR1_CMS;
	TIM1->CR1 |= TIM_CR1_CEN;

	unsigned int r = 0, g = 0, b = 0;

  while(1)
  {
    while (r < 255)
    {
      r += 5;
      delay(delayer);
      TIM1->CCR2 = r;
    }
    while (g < 255)
    {
      g += 5;
      delay(delayer);
      TIM1->CCR3 = g;
    }
    while (b < 255)
    {
      b += 5;
      delay(delayer);
      TIM1->CCR4 = b;
    }

    while (r > 0)
    {
      r -=5;
      delay(delayer);
      TIM1->CCR2 = r;
    }
    while (g > 0)
    {
      g -=5;
      delay(delayer);
      TIM1->CCR3 = g;
    }
    while (b > 0)
    {
      b -=5;
      delay(delayer);
      TIM1->CCR4 = b;
    }
  }

  return 0;
}