Manioc

ar_cond

Nov 23rd, 2018
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  1. // DESCRIPTION: Verilator: Systemverilog example module
  2. // with interface to switch buttons, LEDs, LCD and register display
  3.  
  4. parameter NINSTR_BITS = 32;
  5. parameter NBITS_TOP = 8, NREGS_TOP = 32;
  6. module top(input  logic clk_2,
  7.            input  logic [NBITS_TOP-1:0] SWI,
  8.            output logic [NBITS_TOP-1:0] LED,
  9.            output logic [NBITS_TOP-1:0] SEG,
  10.            output logic [NINSTR_BITS-1:0] lcd_instruction,
  11.            output logic [NBITS_TOP-1:0] lcd_registrador [0:NREGS_TOP-1],
  12.            output logic [NBITS_TOP-1:0] lcd_pc, lcd_SrcA, lcd_SrcB,
  13.              lcd_ALUResult, lcd_Result, lcd_WriteData, lcd_ReadData,
  14.            output logic lcd_MemWrite, lcd_Branch, lcd_MemtoReg, lcd_RegWrite);
  15.  
  16.  
  17.   logic [1:0] clk_1;
  18.   logic [1:0] tempo;
  19.   always_ff @(posedge clk_2) begin
  20.     clk_1 <= clk_1 + 1;
  21.   end
  22.  
  23.   enum logic {
  24.     indesejada,
  25.     desejada
  26.   } state;
  27.  
  28.   logic reset, diminuir, aumentar, pitu, flag;
  29.   logic [2:0] atual, desejo, espera;
  30.   logic [3:0] counter;
  31.   always_comb begin
  32.     reset <= SWI[7];
  33.     diminuir <= SWI[0];
  34.     aumentar <= SWI[1];
  35.   end
  36.  
  37.   always_ff @(posedge clk_1[1] or posedge reset) begin
  38.     if(reset) begin
  39.       counter <= 0;
  40.       pitu <= 0;
  41.       flag <= 0;
  42.       atual <= 0;
  43.     end
  44.     else begin
  45.       counter <= counter + 1;
  46.       if(counter == 10 && !flag) begin
  47.         counter <= 0;
  48.         pitu <= 1;
  49.         flag <= 1;
  50.       end
  51.  
  52.       desejo <= desejo - diminuir + aumentar;
  53.       unique case(state)
  54.         indesejada:
  55.           if(counter[0]) begin
  56.             if(atual < desejo) atual <= atual + 1;
  57.             else if(atual > desejo) atual <= atual - 1;
  58.             else state <= desejada;
  59.           end
  60.         desejada:
  61.           if(diminuir^aumentar) state <= indesejada;
  62.           else if(atual == 7) begin
  63.             espera <= espera + 1;
  64.             if(espera == 4) pitu <= 0;
  65.           end
  66.  
  67.       endcase
  68.     end
  69.   end
  70.   always_comb begin
  71.     LED[7] <= clk_1[1];
  72.     LED[6:4] <= atual;
  73.     LED[3] <= pitu;
  74.     LED[2:0] <= desejo;
  75.   end
  76. endmodule
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