ar_cond

// DESCRIPTION: Verilator: Systemverilog example module
// with interface to switch buttons, LEDs, LCD and register display

parameter NINSTR_BITS = 32;
parameter NBITS_TOP = 8, NREGS_TOP = 32;
module top(input  logic clk_2,
           input  logic [NBITS_TOP-1:0] SWI,
           output logic [NBITS_TOP-1:0] LED,
           output logic [NBITS_TOP-1:0] SEG,
           output logic [NINSTR_BITS-1:0] lcd_instruction,
           output logic [NBITS_TOP-1:0] lcd_registrador [0:NREGS_TOP-1],
           output logic [NBITS_TOP-1:0] lcd_pc, lcd_SrcA, lcd_SrcB,
             lcd_ALUResult, lcd_Result, lcd_WriteData, lcd_ReadData,
           output logic lcd_MemWrite, lcd_Branch, lcd_MemtoReg, lcd_RegWrite);


  logic [1:0] clk_1;
  logic [1:0] tempo;
  always_ff @(posedge clk_2) begin
    clk_1 <= clk_1 + 1;
  end

  enum logic {
    indesejada,
    desejada
  } state;

  logic reset, diminuir, aumentar, pitu, flag;
  logic [2:0] atual, desejo, espera;
  logic [3:0] counter;
  always_comb begin
    reset <= SWI[7];
    diminuir <= SWI[0];
    aumentar <= SWI[1];
  end

  always_ff @(posedge clk_1[1] or posedge reset) begin
    if(reset) begin
      counter <= 0;
      pitu <= 0;
      flag <= 0;
      atual <= 0;
    end
    else begin
      counter <= counter + 1;
      if(counter == 10 && !flag) begin
        counter <= 0;
        pitu <= 1;
        flag <= 1;
      end

      desejo <= desejo - diminuir + aumentar;
      unique case(state)
        indesejada:
          if(counter[0]) begin
            if(atual < desejo) atual <= atual + 1;
            else if(atual > desejo) atual <= atual - 1;
            else state <= desejada;
          end
        desejada:
          if(diminuir^aumentar) state <= indesejada;
          else if(atual == 7) begin
            espera <= espera + 1;
            if(espera == 4) pitu <= 0;
          end

      endcase
    end
  end
  always_comb begin
    LED[7] <= clk_1[1];
    LED[6:4] <= atual;
    LED[3] <= pitu;
    LED[2:0] <= desejo;
  end
endmodule